Analytical Algorithms for Faulty Effects Analysis

Single and multiple upsets errors
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 26)

Reconfigurable FPGAs are very appealing as a replacement of ASICs for low-volume designs. FPGAs offer performance levels close to that of ASICs, plenty of resources to implement even very complex systems, as well as the possibility of performing in-the-field-reprogrammability.


Fault Injection Memory Element Logic Resource FPGA Device Logic Topology 
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  1. 1.
    E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa, A. Salazar, Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing, presented at the MAPLD Conference, Sept. 1999.Google Scholar
  2. 2.
    M. Ceschia, A. Paccagnella, S. -C. Lee, C. Wan, M. Bellato, M. Menichelli, A. Papi, A. Kaminski, J. Wyss, Ion Beam Testing of ALTEERA APEX FPGAs, NSREC 2002 Radiation Effects Data Workshop Record, Phoenix, AZ, July 2002.Google Scholar
  3. 3.
    R. Katz, K. LaBel, J. J. Wang, B. Cronquist, R. Koga, S. Penzin, G. Swift, Radiation Effects on Current Field Programmable Technologies, IEEE Transaction on Nuclear Science, Vol. 44, No. 6, Dec. 1997, pp. 1945–1956.CrossRefGoogle Scholar
  4. 4.
    D. K. Pradhan, Fault-Tolerant Computer System Design, Upper Saddle River, NJ, Prentice-Hall, 1996.Google Scholar
  5. 5.
    F. Lima, C. Carmichael, J. Fabula, R. Padovani, R. Reis, A Fault Injection Analysis of Virtex FPGA TMR Design Methodology, in Proceedings IEEE European Conference on Radiation and Its Effect on Component and System, 2001, pp. 275–282.Google Scholar
  6. 6.
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante, On the Evaluation of SEUs Sensitiveness in SRAM-Based FPGAs, IEEE 10th On-Line Testing Symposium, 2004, pp. 115–120.Google Scholar
  7. 7.
    M. Alderighi, S. D’Angelo, M. Mancini, G. R. Sechi, A Fault Injection Tool for SRAM-Based FPGA, 9th IEEE On-Line Testing Symposium, 2003, pp. 129–133.Google Scholar
  8. 8.
    P. Sundararajan, B. Blodget, Estimation of Mean Time Between Failure Caused by Single Event Upset, Xilinx Application notes, XAPP559, Jan. 2005.Google Scholar
  9. 9.
    G. Asadi, M. B. Tahoori, An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs, presented at the MAPLD Conference, 2004.Google Scholar
  10. 10.
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori, Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs, IEEE Transaction on Nuclear Science, Vol. 50, No. 6, Dec. 2003, pp. 2088–2094.CrossRefGoogle Scholar
  11. 11.
    C. Y. Lee, An Algorithm for Path Connections and Its Application, IRE Transaction on Electronic Computers, Vol. 10, No. 3, Sept. 1961, pp. 346–365.CrossRefGoogle Scholar
  12. 12.
    A. G. M. Swift, S. M. Guertin, In-Flight Observations of Multiple-Bit Upset in DRAMs, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, Dec. 2000, pp. 2386–2391.CrossRefGoogle Scholar
  13. 13.
    B. R. Koga, K. B. Crawford, P. B. Grant, W. A. Kolasinski, D. L. Leung, T. J. Lie, D. C. Mayer, S. D. Pinkerton, T. K. Tsubota, Single Ion Induced Multiple-Bit Upset in IDT 256K SRAMs, in Proceedings 2nd Euro Conference on Radiation and Its Effects on Components and Systems, St. Malo, France, Sept. 1993, pp. 485–489.Google Scholar
  14. 14.
    C. R. Koga, J. George, G. Swift, C. Yui, L. Edmonds, C. Carmichael, T. Langley, P. Murray, K. Lanes, M. Napier, Comparison of Xilinx Virtex-II FPGA SEE Sensitiveness to Protons and Heavy Ions, IEEE Transactions on Nuclear Science, Vol. 51, No. 5, Oct. 2004, pp. 2825–2833.CrossRefGoogle Scholar
  15. 15.
    D. H. Quinn, P. Graham, J. Krone, M. Caffrey, S. Rezgui, Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs, IEEE Transactions on Nuclear Science, Vol. 52, No. 6, Dec. 2005, pp. 2455–2461.CrossRefGoogle Scholar
  16. 16.
    B. Bridgford, C. Carmichael, C. W. Tseng, Correcting Single-Event Upsets in Virtex-II Platform FPGA Configuration Memory, Xilinx Application Notes, XAPP779, Feb. 19, 2007.Google Scholar
  17. 17.
    L. Sterpone, M. Violante, A New Analytical Approach to Estimate the Effects of SEUs in TMR Architecture Implemented Through SRAM-Based FPGAs, IEEE Transactions on Nuclear Science, Vol. 52, No. 6, Part 1, Dec. 2005, pp. 2217–2223.CrossRefGoogle Scholar
  18. 18.
    “TMRTool User Guide”, Xilinx User Guide UG156, 2004.Google Scholar

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