Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. This research describes Toffoli Gate (TG) implementations of conventional Binary Coded Decimal (BCD) adders, adders for Quick Addition of Decimals (QAD), and carry select BCD adders suitable for multi-digit addition. For an N-digit fast adder, partial parallel processing is done on all digits in the decimal domain. Such high-speed BCD adders find application in realtime processors and internet-based computing. An analysis of delay normalized to a TG and quantum cost of BCD adders is presented. Implementations using TGs and Fredkin Gates (FRGs) are compared based on quantum cost, number of gates, garbage count and delay, and the results are tabulated.
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References
R. Landauer, ‘Irreversibility and Heat Generation in the Computational Process’, IBM Journal of Research Development, 5, 1961, 183–191
C. Bennett, ‘Logical Reversibility of Computation’, IBM Journal of Research and Development, 17, 1973, 525–532
Md. Hafiz Hasan Babu and A. R. Chowdhury, ‘Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder’, VLSI Design 2005, Jan. 2005, Kolkata, India, pp. 255–260
H. Thapliyal, S. Kotiyal, and M. B Srinivas, ‘Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format’, 19th VLSI Design 2006, Jan. 2006, Hyderabad, India, pp. 387–392
R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi, ‘Improved Reversible Logic Implementation of Decimal Adder’, IEEE 11th VDAT Symposium, Aug. 2007, Kolkata, India
M. Haghparast and K. Navi, ‘A Novel Reversible BCD Adder for Nanotechnology Based Systems’, American Journal of Applied Sciences, 5(3), 2008, 282–288, ISSN 1546–9239
E. Fredkin and T. Toffoli, ‘Conservative Logic’, International Journal of Theoretical Physics, 21, 1982, 219–253
R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi, ‘Performance Analysis of Reversible Fast Decimal Adders’, International Conference on Computer Science and Applications, Oct. 2007, San Francisco, USA, pp. 234–239
R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi, ‘Quick Addition of Decimals Using Reversible Conservative Logic’, 15th International Conference on Advanced Computing & Communication ADCOM 2007 18–21 December 2007, IIT Guwahati, India, pp. 191–196
R. Feynman, ‘Quantum Mechanical Computers’, Optical News, 1985, Claydon, Ipswich, pp. 11–20
D. Maslov, ‘Reversible Logic Synthesis’, Ph.D. Dissertation, Computer Science Department, University of New Brunswick, Canada, Oct. 2003
P. Gupta, A. Agrawal, and N. K. Jha, ‘An Algorithm for Synthesis of Reversible Logic Circuits’, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 25(11), Nov. 2006, 2317–2330
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James, R.K., Poulose Jacob, K., Sasi, S. (2009). Reversible Binary Coded Decimal Adders using Toffoli Gates. In: Ao, SI., Rieger, B., Chen, SS. (eds) Advances in Computational Algorithms and Data Analysis. Lecture Notes in Electrical Engineering, vol 14. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8919-0_9
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DOI: https://doi.org/10.1007/978-1-4020-8919-0_9
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