A New Simulation Approach to Investigate Avalanche Behavior

  • I. Pawel
  • R. Siemieniec


Experiments revealed a dependence of sustained avalanche current on epitaxial layer structure, ambient temperature and chip size. With higher on-resistance, the avalanche current normally increases as well. A new mixed-mode simulation model proposed before explained the dependencies of avalanche current on device structure due to inherent instabilities. In this work, the simulation model was extended to explain found dependencies of avalanche current on chip size and therefore the chip layout and chosen external gate resistance.


Critical Current Chip Size Drain Source Voltage Power MOSFETs Gate Resistance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    I. Pawel, R. Siemieniec, M. Rösch, F. Hirler, C. Geissler, A. Pugatschow and L.J. Balk “Design of Avalanche Capability of Power MOSFETs by Device Simulation”, inProc. EPE 2007, 2007Google Scholar
  2. [2]
    R. Siemieniec, F. Hirler, A. Schlögl, M. Rösch, N. Soufi-Amlashi, J. Ropohl and U. Hiller “A new fast and rugged 100 V power MOSFET”, inProc. EPE-PEMC 2006, 2006Google Scholar
  3. [3]
    K. Fischer and K. Shenai “Electrothermal Effects During Unclamped Inductive Switching (UIS) of Power MOSFETs” IEEE Transactions on Electron Devices, 1997, 44, 874-878,CrossRefGoogle Scholar
  4. [4]
    A.I. Deckelmann, G.K. Wachutka, F. Hirler, J. Krumrey and R. Henninger “Avalanche Breakdown Capability of Power DMOS Transistors and the Wunsch-Bell Relation” Microelectronics Reliability, 2003, 43, 1895-1900CrossRefGoogle Scholar
  5. [5]
    A. Vrbicky, D. Donoval, J. Marek, A. Chvala and P. Beno “Analysis of Electro-Thermal Behaviour of DMOS Transistor Structure during UIS Test” Proc. ISPS, 2006Google Scholar
  6. [6]
    K. Chinnaswamy, P. Khandelwal, M. Trivedi and K. Shenai “Unclamped Inductive Switching Dynamics in Lateral and Vertical Power DMOSFETs” Proc. IAS, 1999Google Scholar
  7. [7]
    V. Vaschenko, Y. Martynov and V. Sinkevitch “Simulation of Avalanche Injection Filamentation in MOSFETs and IGBTs” in Proc. ESSDERC, 1997Google Scholar
  8. [8]
    P. Rossel, H. Tranduc, D. Montcoqut, G. Charitat and I. Pagés “Avalanche Characteristics of MOS Transistors” in Proc. MIEL, 1997Google Scholar
  9. [9]
    A.I. Deckelmann, G.K. Wachutka, F. Hirler, J. Krumrey and R. Henninger “Failure of Multiple-Cell Power DMOS Transistors in Avalanche Operation” in Proc. ESSDERC, 2003Google Scholar
  10. [10]
    G. Hurkx and N. Koper “A Physics-Based Model for the Avalanche Ruggedness of Power Diodes” in Proc. ISPSD, 1999Google Scholar
  11. [11]
    K. Kawamoto, S. Takahashi, S. Fujino and I. Shirakawa “A No-Snapback LDMOSFET With Automotive ESD Endurance” IEEE Transactions on Electron Devices, 2002, 49, 2047-2053CrossRefGoogle Scholar
  12. [12]
    I. Pawel, R. Siemieniec, M. Rösch, F. Hirler and R. Herzer “Experimental Study and Simulations on Two Different Avalanche Modes in Trench Power MOSFETs”, IET Circuits, Devices & Systems, in pressGoogle Scholar
  13. [13]
    Synopsys, Inc,. MEDICITM User Guide, 2006Google Scholar
  14. [14]
    M.P. Shaw, V. Mitin, E. Schöll and H. Grubin “The Physics of Instabilities in Solid State Electron Devices” New York, Plenum Press, 1992Google Scholar
  15. [15]
    M. Denison “Single Stress Safe Operating Area of DMOS Transistors integrated in Smart Power Technologies”, PhD thesis, University of Bremen, 2004Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2008

Authors and Affiliations

  • I. Pawel
    • 1
  • R. Siemieniec
    • 1
  1. 1.Infineon Technologies Austria AGA-9500 VillachAustria

Personalised recommendations