Catapult Synthesis: A Practical Introduction to Interactive C Synthesis

Abstract

The design complexity of today's electronic applications has outpaced traditional RTL methods which involve time consuming manual steps such as micro-architecture definition, handwritten RTL, simulation, debug and area/speed optimization through RTL synthesis. The Catapult® Synthesis tool moves hardware designers to a more productive abstraction level, enabling the efficient design of complex ASIC/FPGA hardware needed in modern applications. By synthesizing from specifications in the form of ANSI C++ programs, hardware designers can now leverage a precise and repeatable process to create hardware much faster than with conventional manual methods. The result is an error-free flow that produces accurate RTL descriptions tuned to the target technology.

This paper provides a practical introduction to interactive C synthesis with Catapult® Synthesis. Our introduction gives a historical perspective on high-level synthesis and attempts to demystify the stereotyped views about the scope and applicability of such tools. In this part we will also take a look at what is at stake – beyond technology – for successful industrial deployment of a high-level synthesis methodology. The second part goes over the Catapult workflow and compares the Catapult approach with traditional manual methods. In the third section, we provide a detailed overview on how to code, constrain and optimize a design with the Catapult Synthesis tool. The theoretical concepts revealed in this section will be illustrated and applied in the real-life case study presented in the fourth part, just prior to the concluding section.