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Assertions and the Verification Landscape

This chapter presents an overview of assertions and their use throughout the product development lifecycle, including hardware verification, debug and monitoring. Assertions use in the areas of simulation, emulation and formal verification are overviewed. Assertion checkers and checker generators, two central themes in this book, are also presented. An introduction to temporal logic is also performed, given the strong foundations of assertion languages in this area. With the origins of assertion residing in the software side, it is only fitting to begin the chapter with a survey of assertions in software.

Keywords

Model Check Clock Cycle Linear Temporal Logic Execution Trace Liveness Property 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science + Business Media B.V 2008

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