Introduction

Even though it becomes possible to realize more and more functionalities using digital circuits, the design of analog circuits still has its important role in the design of numerous systems on chip that are produced nowadays. Analog cells are extensively used in analog-to-digital and digital-to-analog interfaces in mixed-mode systems, as well as for the implementation of different analog functions such as amplifiers or integrators.

With the advances in technology development and the use of submicron and sub-100 nm CMOS processes, digital circuits have become faster and more precise, occupying at the same time smaller surfaces. This imposes more severe specifications in terms of gain, speed and acceptable surface for the analog counterparts. Hence, the design of analog cells becomes a very sophisticated task, since modern technologies introduce two major difficulties: larger parasitic capacitances (since oxide thickness decreases) and smaller output resistances (due to short channel-effects and drain induced barrier lowering DIBL). In other words, a common analog design task nowadays is to design a circuit that will achieve the demanding specifications, using a smaller voltage headroom (as the supply voltage headroom is also reduced) and transistors that have more parasitic effects and smaller intrinsic gain. Thus, the eternal question “How to size analog circuits to achieve the required performances?” arises with even more importance than before.