A 0.4 ps-RMS-Jitter 1–3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification

The trend toward high frequency and broadband digital communication has increased the demand for low jitter, low phase noise clock generation circuits. Due to limited bandwidth on the printed-circuit board, the high cost of high frequency clock source and excessive power dissipation caused by routing high speed clock off-chip, it is necessary to integrate clock multiplier PLLs on-chip.

For high performance DACs with GHz sampling frequency, the input date-rate is usually several times slower, and an on-chip digital interpolation filter is used to select the desired Nyquist zone before the signal is converted to analog domain, leading to relaxed requirements and reduced signal loss of the output anti-aliasing filter. These DACs require clock multiplier PLLs that can provide both low jitter and wide tuning range to satisfy a wide range of customer provided data-rates. Other applications such as multi-standard transceiver and multi-data-rate SERDES also require PLLs with both low jitter/phase-noise and wide tuning range.

The high speed SAR ADC described in the previous chapter requires a 2.5 GHz internal clock, from which the ADC sampling clock is also derived. This clock should have sufficiently low jitter (much less than 3 psrms to affect the SNR negligibly for input signal frequency up to the Nyquist) and the frequency should also be widely adjustable to facilitate debugging of the ADC.