Advertisement

Hamming code for Flash memories

  • R. Micheloni
  • A. Marelli
  • R. Ravasio

Keywords

Parity Matrix Flash Memory External Memory Cache Memory Single Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Bibliography

  1. C. L. Chen, “Symbol Error-Correcting Codes for Computer Memory Systems” in IEEE Transactions on Computers, Vol. 46, February 1992.Google Scholar
  2. C. L. Chen, “Symbol Error Correcting Codes for Memory Applications” in IEEE Proceedings of FTCS, 1996.Google Scholar
  3. C. L. Chen, M. Y. Hsiao, “Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art-Review” in IBM Journal of Research and Development, March 1984.Google Scholar
  4. A. A. Davydov, L. M. Tombak, “An Alternative to the Hamming Code in the Class of SEC-DED Codes in Semiconductor Memory” in IEEE Transactions on Information Theory, Vol. 37, May 1991.Google Scholar
  5. I. Dror, M. Avraham, B. Dulgunov, E. Fumbarov, “Compact High-Speed Single-Bit Error-Correction Circuit” in US Patent US2005/0160350 A1, July 2005.Google Scholar
  6. F. Fummi, D. Sciuto, C. Silvano, “Automatic Generation of Error Control Codes for Computer Applications” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, July 1998.Google Scholar
  7. S. Gregori, A. Cabrini, O. Khouri, G. Torelli, “On-Chip Error Correcting Techniques for New-Generation Flash Memories” in Proceedings of the IEEE, Vol. 91, April 2003.Google Scholar
  8. S. Gregori, O. Khuori, R. Micheloni, G. Torelli, “An Error Control Code Scheme for Multilevel Flash Memories”, 2001 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2001), San Jose, California (USA), August 2001, pp. 45–49.Google Scholar
  9. M. Harmada, E. Fujiwara, “A Class of Error Control Codes for Byte Organized Memory Systems - SbEC-(Sb+S)ED Codes” in IEEE Transactions on Computers, Vol. 46, January 1997.Google Scholar
  10. T. Ken, T. Tomoharu, T. Toru, “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories” in IEEE Journal of Solid State Circuits, Vol. 33, August 1998.Google Scholar
  11. M. Lasser, “Method of Managing a Multi-Bit-Cell Flash Memory” in US Patent US2006/0004952 A1, January 2006.Google Scholar
  12. P. Makumber, “Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit” in IEEE Transactions on Computers, Vol. 42, December 1993.Google Scholar
  13. P. Mazumder, “Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit” in IEEE Transactions on Computers, Vol. 42, December 1993.Google Scholar
  14. D. N. Nguyen, S. M. Guertin, A. H. Johnston, “Radiation Effects on Advanced Flash Memories” in IEEE Transactions on Nuclear Science, Vol. 46, December 1999.Google Scholar
  15. E. Ou, W. Yang, “Fast Error-Correcting Circuits for Fault-Tolerant Memory”, in IEEE International Workshop on Memory Technology, Design and Testing, 2004.Google Scholar
  16. L. Penzo, D. Sciuto, C. Silvano, “Construction Tecniques for Systematic SED-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems” in IEEE Transactions on Information Theory, Vol. 41, March 1995.Google Scholar
  17. B. Polianskikh, Z. Zilic, “Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection” in Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic, 2002.Google Scholar
  18. D. Rossi, C. Metra, B. Riccò, “Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories” in IEEE International On-Line Testing Workshop, 2002.Google Scholar
  19. M. Spica, “Do We Need Anything More than Single Bit Error Correction (ECC)?” in IEEE International Workshop on Memory Technology, Design and Testing, 2004.Google Scholar
  20. T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, “A Compact On-Chip ECC for Low Cost Flash Memories” in IEEE Journal of Solid-State Circuits, Vol. 32, May 1997.Google Scholar
  21. T. Toru, T. Ken, S. Riichiro, A. Seiichi, W. Hiroshi, H. Gertjan, S. Kazuhiro, S. Shinji, T. Yuji, O. Kazunori, “A Compact On-Chip ECC for low Cost Flash Memories” in IEEE Journal of Solid State Circuits, Vol. 32, May 1997.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • R. Micheloni
    • 1
  • A. Marelli
    • 1
  • R. Ravasio
    • 1
  1. 1.Qimonda Italy srl Design Center VimercateItaly

Personalised recommendations