Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques

Technology scaling dramatically increases the sensitivity of the semiconductor devices to radiation. Due to large number of cells with minimized dimensions, SRAM arrays often are the densest circuitry on a chip. The large bit count contributes to the probability that an ionizing particle will hit a sensitive node in the array and corrupt the stored data. The minimum layout dimensions reduce the storage node capacitance and thus, the critical charge Qcrit that can be injected by radiation and upset the SRAM cell. The shrinking supply voltages reduce the Qcrit even further. These factors contribute to the radiation-induced data errors that complicate building reliable SRAM arrays in nano-scaled technologies.

Radiation can create localized ionization events in the semiconductor devices either directly or as secondary reaction products. Many of these radiation-induced events create enough electron-hole pairs to upset the storage nodes of SRAM cells. Such an upset is called a “soft” error. While such an upset can cause a data error, the device structures are not permanently damaged. If the voltage disturbance on a storage node of an SRAM cell is smaller than the noise margin of that node, the cell will continue to operate properly maintaining its data integrity. However, if the noise margin of a cell is not sufficient to withstand the disturbance caused by ionizing radiation, a “soft” error will result.