Introduction and Motivation
As the process technology continues to scale, the stability of embedded Static Random Access Memories (SRAMs) is a growing concern in the design and test community [1–3]. Maintaining an acceptable Static Noise Margin (SNM) in embedded SRAMs while scaling the minimum feature sizes and supply voltages of the Systems-on-a-Chip (SoC) becomes increasingly challenging. Modern semiconductor technologies push the physical limits of scaling which results in device patterning challenges and non-uniformity of channel doping. As a result, precise control of the process parameters becomes exceedingly difficult and the increased process variations are translated into a wider distribution of transistor and circuit characteristics.
Large SRAM arrays that are widely used as cache memory in microprocessors and application-specific integrated circuits can occupy a significant portion of the die area. In an attempt to optimize the performance/cost ratio of such chips, designers are faced with a dilemma. Large arrays of fast SRAM help to boost the system performance. However, the area impact of incorporating large SRAM arrays into a chip directly translates into a higher chip cost. Balancing these requirements is driving the effort to minimize the footprint of SRAM cells. As a result, millions of minimum-size SRAM cells are tightly packed making SRAM arrays the densest circuitry on a chip. Such areas on the chip can be especially susceptible and sensitive to manufacturing defects and process variations. International Technology Roadmap for Semiconductors (ITRS) [4, 5] predicted “greater parametric yield loss with respect to noise margins” for high density circuits such as SRAM arrays, which are projected to occupy more than 90% of the SoC area in the next 10 years (Figure 1.1).
KeywordsTest Time Table SRAM Cell Automate Test Equipment Technology Scaling March Test
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