Whole-chip ESD protection has become an important reliability issue of CMOS IC’s. Even if there are suitable ESD protection circuits at the input and output pads, the internal circuits are still vulnerable to the ESD damage. The pin-to-pin ESD stress, as shown in Figure 5-1, often causes some unexpected ESD damage located in the internal circuits, rather than the input or output ESD protection circuits. In Figure 5-1, the ESD current is discharged through the internal circuit and may cause random ESD damage in this circuit, as the “Path 1” current flow shown in Figure 5-1. If there is an effective ESD clamp circuit across the VDD and VSS power buses, the ESD current can be discharged through the “Path 2” current flow. Thus, an effective ESD clamp circuit between the power rails is necessary for the protectting of internal circuits against the ESD damage. Clamps can come in many different varieties. A simple diode clamps were already mentioned in Chapter 4 (Figure 4-2).
ESD Clamps can be grouped into two categories: static and transient. The static clamps provide a static or steady-state current and voltage response. A fixed voltage level activates static clamps. As long as the voltage is above this level, the clamp will conduct current. A diode, MOSFET and SCR based clamps are known as static ESD clamps. Transient clamps take advantage of the rapid changes in voltage and/or current that accompanies an ESD event. During this transient, an element is turned on very quickly and slowly turns off. This type of clamp conducts for a fixed time when it is triggered. An RC network determines the time constant. These clamps are typically triggered by very fast events on the supply lines.
Both groups of clamps have their respective advantages and disadvantages. The static clamp typically occupies less space and is composed of fewer elements. If a static clamp falsely triggers while power is applied to the part, it will result in large, steady current and may lead to damage. Transient clamps, on the other hand, can be designed to turn on very quickly and handle larger transient events. The disadvantage is that they will also respond to any fast event, even noise. If they falsely trigger while the part is powered, they could interfere with circuit operation and it is likely that the part will be destroyed. In this chapter, the different designs of ESD clamps are considering and their advantages and disadvantages are discussed in details.
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(2008). ESD Power Clamps. In: ESD Protection Device and Circuit Design for Advanced CMOS Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8301-3_5
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