Abstract
Transaction-level modeling (TLM) allows for the design of virtual prototypes, providing considerably faster simulation speed than RTL models. But combinatorial dependencies are often inexactly modeled in terms of cycle accuracy, leading to imprecise simulation results. If, however, precise results are desired, additional coding and simulation effort is required. As a result, simulation performance drops down. This paper surveys the existing techniques to model combinatorial dependencies in TLM and presents a novel approach based on synchronization layers. Experimental results with SystemC prove our technique to enable higher simulation speed than the surveyed approaches, without inheriting their disadvantages.
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References
ARM Limited (2007) RealView ESL API. http://www.arm.com/products/DevTools/RealViewESLAPIs.html. Accessed 02 February 2007
Black DC, Donovan J (2004) SystemC: From the Ground Up. Kluwer, Dordrecht, The Netherlands
Burton M, Morawiec A (2006) Platform Based Design at the Electronic System Level. Industry Perspectives and Experiences. Springer, Dordrecht, The Netherlands
Cai L, Gajski D (2003) Transaction Level Modeling: An Overview. In: International Conference on Hardware/Software Codesign and System Synthesis. Wiley-IEEE, Hoboken, NJ
Ghenassia F (2005) Transaction-Level Modelling with SystemC. Springer, Dordrecht, The Netherlands
Groetker T, Liao T, Martin S(2002) System Design with SystemC. Kluwer, Dordrecht, The Netherlands
IBM (2001) The CoreConnect Bus Architecture. http://www-01.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_Bus_Architecture. Accessed 21 December 2006
Klingauf W, Guenzel R, Bringmann O, Parfuntseu P, Burton M (2006) GreenBus–A Generic Interconnect Fabric for TLM. In: Design Automation Conference, 2006 43rd ACM/IEEE. ACM, New York
OCP-IP (2006) A SystemC OCP Transaction Level Communication Channel r2.1.3. http://www.ocpip.org/socket/systemc/. Accessed 03 December 2006
Palnitkar S, Parham D (1995) Cycle Simulation Techniques. In: Verilog HDL Conference, 1995. Proceedings. Wiley/IEEE Press, Hoboken, NJ
OSCI TLM WG (2007) TLM Transaction Level Modeling Library, Release 2.0 Draft 2. http://www.systemc.org/downloads/drafts_review. Accessed 05 December 2007
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Guenzel, R., Klingauf, W., Aldis, J. (2008). Combinatorial Dependencies in Transaction Level Models. In: Villar, E. (eds) Embedded Systems Specification and Design Languages. Lecture Notes in Electrical Engineering, vol 10. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8297-9_4
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DOI: https://doi.org/10.1007/978-1-4020-8297-9_4
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