This chapter presents the final conclusions of this research project. The main features and the benchmarking of the prototype ADC are presented in section 6.1. The economic feasibility of the commercial use of the proposed car radio receiver architecture is then discussed in section 6.2.
The design of a high-resolution IF-to-baseband ΣΔADC for AM/FM/ IBOC receivers was the goal of this research. The designed ΣΔquadrature ADC combines the anti-aliasing suppression of a CT loop filter, the low jitter sensitivity of a SC feedback DAC, and the low power consumption of passive mixers for low-IF down-conversion. The achieved 118dB DR in AM mode (3kHz BW) allows the realization of a car radio with a reduced number of external components. The AM ceramic channel selection filter and low-noise/high-linearity VGA required in the traditional AM/FM DSP based receiver architecture are no longer necessary. As a result, the radio’s noise figure and its sensitivity in AM mode are improved. In the proposed radio receiver, most of the AM channel selection is performed in the digital domain.
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References
P. Silva, L. Breems, et al., “A 118dB DR CT IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers”, ISSCC 2006 Digest of Technical Papers, Feb. 2006.
G. Mitteregger, C. Ebner, et al., “A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB”, ISSCC 2006 Digest of Technical Papers, Feb. 2006.
R. Schreier, N. Abaskharoun, et al., “A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz”, ISSCC 2006 Digest of Technical Papers, Feb. 2006.
S. Kwon and F. Maloberti, “A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+”, ISSCC 2006 Digest of Technical Papers, Feb. 2006.
K-S. Lee, S. Kwon and F. Maloberti, “A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSL”, ISSCC 2006 Digest of Technical Papers, Feb. 2006.
Y. Fujimoto, Y. Kanazawa, et al., “A 80/10MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers”, ISSCC 2006 Digest of Technical Papers, Feb. 2006.
R. Brewer, J. Gorbold, et al., “A 100dB SNR 2.5MS/s Output Data Rate ΔΣ ADC”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
A. Bosi, A. Panigada, G. Censura and R. Castello, “An 80MHz 4x Oversampled Cascaded ΔΣ-Pipelined ADC with 75dB DR and 87dB SFDR”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
K. Nguyen, B. Adams, et al., “A 106dB SNR Hybrid Oversampling ADC for Digital Audio”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
P. Morrow, M. Chamarro, et al., “A 0.18 mm 102dB-SNR mixed CT SC audio-band ΣΔ ADC”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
L. Dörrer, F. Kuttner, P. Greco and S. Derksen, “A 3mW 74dB SNR 2MHz CT ΣΔ ADC with a tracking-ADC-Quantizer in 0.13mm CMOS”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
A. Das, R. Hezar, et al., “A 4th-order 86dB CT ΔΣ ADC with two amplifiers in 90nm CMOS”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
P. Fontaine, A. Mohieldin and A. Bellaour, “A Low-Noise Low-Voltage CT ΣΔ Modulator with Digital Compensation of Excess Loop Delay”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
N. Yaghini and D. Johns, “A 43mW CT Complex ΣΔ ADC with 23MHz of Signal Bandwidth and 68.8dB SNDR”, ISSCC 2005 Digest of Technical Papers, Feb. 2005.
L. Breems, “A Cascaded Continuous-Time ΣΔ Modulator with 67dB Dynamic Range in 10MHz Bandwidth”, ISSCC 2004 Digest of Technical Papers, Feb. 2004.
P. Balmelli and Q. Huang, “A 25 MS/s 14 b 200 mW ΣΔ Modulator in 0.18 mm CMOS”, ISSCC 2004 Digest of Technical Papers, Feb. 2004.
B. Putter, “ΣΔ ADC with Finite Impulse Response Feedback DAC”, ISSCC 2004 Digest of Technical Papers, Feb. 2004.
R. Gaggl, M. Inversi and A. Wiesbauer, “A Power Optimized 14-bit SC ΔΣ Modulator for ADSL CO Applications”, ISSCC 2004 Digest of Technical Papers, Feb. 2004.
F. Ying and F. Maloberti, “A Mirror Image Free Two-Path Bandpass ΔΣ Modulator with 72 dB SNR and 86 dB SFDR”, ISSCC 2004 Digest of Technical Papers, Feb. 2004.
Y. Yang, A. Chokhawala, et al., “A 114 dB 68 mW Chopper-Stabilized Stereo Multi-Bit Audio ΔΣA/D Converter”, ISSCC 2003 Digest of Technical Papers, Feb. 2003.
R.H.M. van Veldhoven, “A Triple-Mode Continuous-Time ΣΔ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA200/UMTS Receiver”, ISSCC 2003 Digest of Technical Papers, Feb. 2003.
S. Yan and E. Sánchez-Sinencio, “A Continuous-Time ΣΔ Modulator with 88dB Dynamic Range and 1.1MHz Signal Bandwidth”, ISSCC 2003 Digest of Technical Papers, Feb. 2003.
K. Philips, “A 4.4mW 76dB Complex ΣΔ ADC for Bluetooth Receivers”, ISSCC 2003 Digest of Technical Papers, Feb. 2003.
R. Schreier, J. Lloyd, et al., “A 50mW Bandpass ΣΔ ADC with 333kHz BW and 90dB DR”, ISSCC 2002 Digest of Technical Papers, Feb. 2002.
T. Salo, T. Hollman, et al., “A Dual-Mode 80MHz Bandpass ΔΣ Modulator for a GSM/WCDMA IF-Receiver”, ISSCC 2002 Digest of Technical Papers, Feb. 2002.
S.K. Gupta, T.L. Brooks and V. Fong, “A 64MHz ΣΔ ADC with 105dB IM3 Distortion Using a Linearized Replica Sampling Network”, ISSCC 2002 Digest of Technical Papers, Feb. 2002.
T. Burger and Q. Hueng, “A 13.5mW 185 MSamples/s ΔΣS-Modulator for UMTS/GSM Dual-Standard IF Reception”, ISSCC 2001 Digest of Technical Papers, Feb. 2001.
O. Oliaei, P. Clement and P. Gorisse, “A 5mW ΣΔ Modulator with 84dB Dynamic Range for GSM/EDGE”, ISSCC 2001 Digest of Technical Papers, Feb. 2001.
K. Vleugels, S. Rabii and B.A. Wooley, “A 2.5V Broadband Multi-bit ΣΔ Modulator with 95dB Dynamic Range”, ISSCC 2001 Digest of Technical Papers, Feb. 2001.
Y. Geerts, M. Steyaert and W. Sansen, “A 2.5 MSamples/s Multi-Bit ΔΣ CMOS ADC with 95dB SNR”, ISSCC 2000 Digest of Technical Papers, Feb. 2000.
I. Fujimori, L. Longo, et al., “A 90dB SNR, 2.5MHz Output Rate ADC Using Cascaded Multibit ΔΣ Modulation at 8x Oversampling Ratio”, ISSCC 2000 Digest of Technical Papers, Feb. 2000.
A. Tabatabaei, K. Kaviani and B. Wooley, “A Two-Path ΣΔ Modulator with Extended Noise Shaping”, ISSCC 2000 Digest of Technical Papers, Feb. 2000.
Q. Sandifort, L.J. Breems, C. Dijkmans and H. Schuurmans, “IF-to-Digital Converter for FM/AM/IBOC Radio”, Proceedings of the 29TH European Solid-State Circuit Conference, Estoril, Portugal, Sept. 2003, pp. 707–710.
Catena Radio Design, private communication, 2005.
Philips Semiconductors, private communication, 2006.
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(2008). Conclusion. In: High-Resolution If-To-Baseband ΣΔ Adc For Car Radios. Analog Circuits And Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8164-4_6
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