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Behavioral Type Inference

Part II — Behavioral type inference for system design
  • Jean-Pierre Talpin
  • David Berner
  • Sandeep Kumar Shukla
  • Paul Le Guernic
  • Abdoulaye Gamatié
  • Rajesh Gupta

Abstract

The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design methodologies, that lifts modeling to higher levels of abstraction, and the concept of intellectual property (IP), that promotes reuse of existing components, are essential steps to manage design complexity. However, the issue of compositional correctness arises with these steps. Given components from different manufacturers, designed with heterogeneous models, at different levels of abstraction, assembling them in a correct-by-construction manner is a difficult challenge. We address this challenge by proposing a process algebraic model to support system design with a formal model of computation and serve as a behavioral type system to capture the behavior of system components at the interface level. The proposed algebra is conceptually minimal, equipped with a formal semantics defined in a synchronous model of computation, and supports a scalable notion and a flexible degree of abstraction.

We demonstrate its benefits by considering the type-based synthesis of latency-insensitive protocols. We show that the synthesis of component wrappers can be optimized by the behavioral information carried by interface type descriptions and yields minimized stalls and maximized throughput.

Keywords

Formal Method Finite Impulse Response Finite Impulse Response Filter Proof Obligation Type Inference 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Jean-Pierre Talpin
    • 1
  • David Berner
    • 1
  • Sandeep Kumar Shukla
    • 2
  • Paul Le Guernic
    • 1
  • Abdoulaye Gamatié
    • 1
  • Rajesh Gupta
    • 3
  1. 1.INRIA, project EspressoIRISA, Campus de BeaulieuRennes CedexFrance
  2. 2.Department of Electrical and Computer EngineeringVirginia TechBlacksburgUSA
  3. 3.Department of Computer Science and EngineeringUniversity of California et San DiegoLa JollaUSA

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