Design of Synchronous High-Speed CML Circuits, a PRBS Generator

In this chapter, the design of a high-speed pseudo-random binary sequence (PRBS) generator requiring only a single clock input will be described. The target is to achieve an output bit-rate of at least 40 Gb/s. Detailed circuit simulations using the SiGe technology also used for the 12.5 Gb/s cross-connect switch described in Chapter 4 revealed that a clock to data delay of approximately 15 ps per latch allows the design of a half-rate PRBS core. However, it is not feasible to design the output data multiplexer and output buffer for 40 Gb/s operation. In the simulations, adequate performance was obtained up to approximately 30 Gb/s. To achieve the target 40 Gb/s, an InP HBT technology was selected [1] which results in an improvement in f _T f _max and f _A over the available SiGe technology by a factor of approximately 2 [2]. The design techniques for high bit-rate circuits in SiGe and InP HBT technology are very similar, as will be demonstrated in this chapter.

The maximum speed of digital circuits in a given IC process is often benchmarked on the basis of minimum gate delays, obtained from a ring oscillator. Such a ring oscillator can be built from simple inverters and therefore provides an indication of the maximum achievable speed in a process. However, the design of the ring oscillator tells us little about how more complex gates and latches need to be designed for optimum speed.