Cross-Connect Switch Design

Many aspects that are important in high bit-rate circuit design are brought together in the design of a cross-connect switch IC for routing data in optical networks. The switch matrix, which forms the core of the cross-connect switch IC, is an excellent example showing that optimum performance can only be obtained when circuits and interconnect are optimised together. For the design and optimisation of the signal distribution inside the matrix, extensive use is made of the interconnect models described in Chapter 2 and the device metrics given in Chapter 3.

Other high bit-rate circuits are needed to support the matrix operation, such as input and output buffers and functions for built-in self-testing (e.g., a VCO and a PRBS generator). This chapter will describe the design of the RF path of a crossconnect switch IC that supports 20 differential inputs and 20 differential outputs, at data rates up to 12.5 Gb/s per input. The block diagram of the switch IC is shown in Fig. 1.9. An overview of the main specifications is provided in Table 4.1.

The main focus of this chapter is on the design of the RF signal path. The IC is designed for wire bonding, so all the bondpads must be located on the perimeter of the IC. Because of the large number of bondpads, the die area is bondpad-limited. The IC includes built-in self-test functions, implemented using a PRBS generator plus an error detector, both clocked by an on-chip tuneable LC-VCO. The VCO generates an output frequency of up to 12.5 GHz. When clocked at 12.5 GHz, the PRBS generator outputs a pseudo-random data pattern with a sequence length 2⁷–1 (127 bits) at 12.5 Gb/s. Design aspects of the PRBS generator and VCO will be described in Chapters 6 and 7, respectively. The CMOS configuration interface, built using standard CMOS logic, will not be described.