Abstract
This paper reviews aspects of VLSI fabrication technology and the associated design and design automation techniques to set the stage for the presentation of those papers in physical design and validation that were selected as the most influential DATE publications in the last 10 years.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Johnson, N. L., V. V. Marathe, Bulk CMOS Technology for the HP-41C, Hewlett-Packard Journal, March 1980, see also http://www.hpmuseum.org/journals/hp41/41bc.htm
The International Technology Roadmap for Semiconductors (ITRS), see http://www.itrs.net/
Riley, G. A., Nailing IC’s Together, Flip Chips Dot Com Tutorial 71, February 2007, see http://www.flipchips.com/tutorial71.html, see also IMEC’s website http://www.imec.be.
Pederson, D., A historical review of circuit simulation, IEEE Transaction on Circuits and Systems, Vol. 31, no. 1, Jan. 1984, 103–111.
Breuer, M. A. 1977. Min-cut placement. Journal of Design Automation and Fault Tolerant Computing, Vol. 1, no. 4, 1977, 343–362.
Hall, K. M., An r-dimensional quadratic placement algorithm. Management Science, Vol. 17, no. 3, 1970, 219–229.
Hanan, M. On Steiner’s problem with rectilinear distance. Journal SIAM Applied Mathematics, Vol. 14, no. 2, 1966, 255–265.
Cheng, C. K. Kuh, E.S., Module placement based on resistive network optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 3, no. 3, July 1985, 218–225.
Hashimoto, A., J. Stevens, Wire Routing by Optimizing Channel Assignment within Large Apertures, Proc. 8th Workshop on Design Automation, Atlantic City, US, June 28–30, 1971, pp. 155–169.
Lee, C. Y., An algorithm for path connections and its applications, IRE Transaction on Electronic Computers, Vol. EC-10, 1961. 346–365.
Hightower, D. W., A solution to line-routing problems on the continuous plane, Proc. 6th Annual Conference on Design Automation, 1969, pp. 1–24.
Tarjan, R.E., Depth first search and linear graph algorithms, SIAM Journal on Computing 1, 1972, 146–160.
Ousterhout, J. K., Corner Stitching: A Data Structuring Technique for VLSI Layout Tools, IEEE Transaction on Computer Aided Design, Vol. 3, no. 1, 1984, 87–100.
Bentley, J.L., D. Haken and R. Hon, Fast geometric algorithms for VLSI tasks, IEEE CompCon Spring ‘80, 1980, 88–92.
Kirkpatrick, S., C. D. Gelatt Jr., and M. P. Vecchi, Optimization by simulated annealing, Science, Vol. 220, no. 4598, 1983, 671–680.
Fishburn, J.P., A. E. Dunlop. Tilos: A posynomial programming approach to transistor sizing. In IEEE Intl. Conf. on CAD, pp. 326–328, 1985.
Schaper, R. L., D. I. Amey, Improved Electrical Performance Required for Future MOS Packaging, IEEE Transaction on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-6, no. 3, 1983, 283–289.
Van Ginneken, L. P. P. P., Buffer placement in distributed RC-tree network for minimal Elmore delay, in Proc. IEEE Int. Symp. Circuits Systems, New Orleans, LA, 1990, pp. 865–868.
Sutherland, I. E., R. F. Sproull, Logical Effort: Designing for Speed on the Back of an Envelope, Proc. of the 1991 UC Santa Cruz Conf. on Advanced Research in VLSI, MIT-Press, Cambridge, MA, USA, 1991, pp. 1–16.
Orshansky, M., L. Milor, P. Chen, K. Keutzer, C. Hu, Impact of Systematic Spatial Intra-Chip Length Variability on Performance of High Speed Circuits, IEEE/ACM Intern. Conf. on CAD (ICCAD), 2000, pp. 62–67.
Visweswariah, C., Death, Taxes and Failing Chips, Proc. of the 40th Conf. on Design Automation, ACM Press, New York, 2003, pp. 343–347.
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer
About this chapter
Cite this chapter
Jess, J. (2008). Physical Design and Validation. In: Lauwereins, R., Madsen, J. (eds) Design, Automation, and Test in Europe. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6488-3_25
Download citation
DOI: https://doi.org/10.1007/978-1-4020-6488-3_25
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-6487-6
Online ISBN: 978-1-4020-6488-3
eBook Packages: EngineeringEngineering (R0)