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MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis

  • Robert P. Dick
  • Niraj K. Jha
  • Robert P. Dick
  • Niraj K. Jha

Abstract

In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrated circuit. Given a system specification consisting of multiple periodic task graphs as well as a database of core and integrated circuit characteristics, MOCSYN synthesizes real-time heterogeneous single-chip hardware-software architectures using an adaptive multiobjective genetic algorithm that is designed to escape local minima. The use of multiobjective optimization allows a single system synthesis run to produce multiple designs which trade off different architectural features. Integrated circuit price, power consumption, and area are optimized under hard real-time constraints. MOCSYN differs from previous work by considering problems unique to single-chip systems. It solves the problem of providing clock signals to cores composing a system-on-a-chip. It produces a bus structure which balances ease of layout with the reduction of bus contention. In addition, it carries out floorplan block placement within its inner loop allowing accurate estimation of global communication delays and power consumption.

Keywords

Multiobjective Optimization Embed System Task Assignment Clock Frequency Task Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2008

Authors and Affiliations

  • Robert P. Dick
  • Niraj K. Jha
  • Robert P. Dick
    • 1
  • Niraj K. Jha
    • 1
  1. 1.Department of Electrical Engineering PrincetonUniversity PrincetonNew Jersey

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