Abstract
We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.
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Eles, P., Kuchcinski, K., Peng, Z., Doboli, A., Pop, P. (2008). Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. In: Lauwereins, R., Madsen, J. (eds) Design, Automation, and Test in Europe. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6488-3_2
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DOI: https://doi.org/10.1007/978-1-4020-6488-3_2
Publisher Name: Springer, Dordrecht
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