Rich applications in handheld devices such as navigation and Internet access have witnessed the rapid evolution of wireless services from traditionally simple voice/text, to recently multimedia. As shown in Figure 1-1, the current wireless services cover a wide range of data rate related to distance, continuously trending toward offering the best connectivity. It will not be surprising that, in the 4th generation (4G), the portable devices will become a universal terminal [1.1]. From the viewpoint of integrated-circuit (IC) design, however, a one-fits-all “analog” front-end is undoubtedly thorny to be realized. The four dimensions of IC innovation, i.e., technology, devices, circuits and system architecture, will face unprecedented design challenges. This chapter will present a glimpse into them.
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References
Y. Neuvo, “Cellular Phones as Embedded Systems,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 32-37, Feb. 2004.
J. McNeill, M. Colin and B. Larivee, “A Split-ADC Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC,” IEEE International Solid- State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 276-277, Feb. 2005.
G. K. Fedder and T. Mukherjee, “Tunable RF and Analog Circuits Using On-Chip MEMS Passive Components,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 390-391, Feb. 2005.
M.-A. Dubois, C. Billard, C. Muller, G. Parat and P. Vincent, “Integration of High-Q BAW Resonators and Filters Above IC,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 392-393, Feb. 2005.
B. Razavi, “A 60GHz Direct-Conversion CMOS Receiver,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 400-401, Feb. 2005.
P.-C. Huang, M.-D. Tsai, H. Wang and C.-H. Chen “A 114GHz VCO in 0.13μm CMOS Technology,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 404-405, Feb. 2005.
D. Chin, “Nanoelectronics for an Ubiquitous-Information society,” IEEE Inter- national Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 22-26, Feb. 2005.
“The International Technology Roadmap for Semiconductors (ITRS) - RF and Analog/Mixed-Signal Technologies for Wireless Communications,” 2004. [1.Online] Available: http://www.itrs.net/Common/2004Update/2004_04_Wireless.pdf
H. Huang and E. K. F. Lee, “Design of Low-Voltage CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” IEEE Journal of Solid-State Circuits (JSSC), vol. 36, no. 8, pp. 1168-1177, Aug. 2001.
M. Ozgun, Y. Tsividis and G. Burra, “Dynamically Power-Optimized Channel- Select Filter for Zero-IF GSM,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 504-505, Feb. 2005.
S. Chatterjee, Y. Tsividis and P. Kinget, “A 0.5V Filter with PLL-Based Tuning in 0.18μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 506-507, Feb. 2005.
G. Vemulapalli, P. K. Hanumolu, Y.-J. Kook and U. K. Moon, “A 0.8-V Accurately Tuned Linear Continuous-Time Filter,” IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 9, pp. 1972-1977, Sept. 2005.
T. Ueno and T. Itakura, “A 0.9V 1.5mW Continuous-Time ΔΣ Modulator for WCDMA,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 78-79, Feb. 2004.
L. Dorrer, F. Kuttner, P. Greco and S. Derksen, “A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a Tracking-ADC-Quantizer in 0.13μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 492-493, Feb. 2005.
T. Nagai, H. Satou, H. Yamazaki and Y. Watanabe, “A 1.2V 3.5mW ΔΣ Modulator with a Passive Current Summing Network and a Variable Gain Function,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 494-495, Feb. 2005.
P. Fontaine, A. N. Mohiedin and A. Bellaouar, “A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop Delay,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 498-499, Feb. 2005.
A. Das, R. Hezar, R. Byrd, G. Gornez and B. Haroun, “A 4th-Order 86dB CT ΔΣ ADC with Two Amplifiers in 90nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 496-498, Feb. 2005.
G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigne, E. Romani, A. Melodia and V. Mellimi, “A 14b 20mW CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 62-63, Feb. 2006.
K.-P. Pun, S. Chatterjee and P. Kinget, “A 0.5V 74dB SNDR 25 kHz CT ΔΣ Modulator with Return-to-Open DAC,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 72-73, Feb. 2006.
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(2007). Introduction. In: Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6433-3_1
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