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Charge Trapping Phenomena in Single Electron NVM SOI Devices Fabricated by a Self-Aligned Quantum DOT Technology

  • Alexei N. Nazarov
  • Vladimir S. Lysenko
  • Xiaohui Tang
  • Nicolas Reckinger
  • Vincent Bayot
Part of the NATO Science for Peace and Security Series B: Physics and Biophysics book series (NAPSB)

Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id - Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.

Keywords

Gate Voltage Drain Current Charge Trap Charge Trapping Threshold Voltage Shift 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2007

Authors and Affiliations

  • Alexei N. Nazarov
    • 1
  • Vladimir S. Lysenko
    • 1
  • Xiaohui Tang
    • 2
  • Nicolas Reckinger
    • 2
  • Vincent Bayot
    • 2
  1. 1.Institute of Semiconductor PhysicsNational Academy of Sciences of UkraineUkraine
  2. 2.Microelectronics Laboratory (DICE)Université catholique de LouvainBelgium

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