Charge Trapping Phenomena in Single Electron NVM SOI Devices Fabricated by a Self-Aligned Quantum DOT Technology
Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id - Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.
KeywordsGate Voltage Drain Current Charge Trap Charge Trapping Threshold Voltage Shift
Unable to display preview. Download preview PDF.