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A Comparative Study Regarding a Memory Hierarchy with the CDLR SPEC 2000 Simulator

  • O. Novac
  • M. Vlădutiu
  • St Vari Kakas
  • Mihaela Novac
  • M. Gordan
Conference paper

Abstract

We have built a simulator named, CDLR SPEC 2000. This simulator is based on traces for systems with cache memories. With CDLR SPEC 2000 program we can study, for a memory hierarcy, the next parameters: maping function, block size, writing strategies, replacement algoritm, size of cache memory, number of cache sets (for the set associative caches), number of words form a block. The simulator can be used for the study of cache memory behaviour. Also the CDLR SPEC 2000 program, introduce the calculus of CDLR of a memory hierarchy. A common metric used for the assessment of overall reliability, in a memory hierarchy is the Mean Time To Failure (MTTF), but it doesn’t take into account for the time of data storage in each level. We propose another metric, Cache Data Loss Rate (CDLR), for this reason. We will derive a recurrent formula for computing CDLR, and we will validate it by computer simulation.

Keywords

Block Size Read Time Replacement Policy Memory Hierarchy Cache Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer 2007

Authors and Affiliations

  • O. Novac
    • 1
  • M. Vlădutiu
    • 2
  • St Vari Kakas
    • 1
  • Mihaela Novac
    • 3
  • M. Gordan
    • 3
  1. 1.Department of ComputersUniversity of Oradea
  2. 2.Department of Computers, “Politehnica”University of Timişoara
  3. 3.Department of ElectrotechnicsUniversity of Oradea

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