A Comparative Study Regarding a Memory Hierarchy with the CDLR SPEC 2000 Simulator
We have built a simulator named, CDLR SPEC 2000. This simulator is based on traces for systems with cache memories. With CDLR SPEC 2000 program we can study, for a memory hierarcy, the next parameters: maping function, block size, writing strategies, replacement algoritm, size of cache memory, number of cache sets (for the set associative caches), number of words form a block. The simulator can be used for the study of cache memory behaviour. Also the CDLR SPEC 2000 program, introduce the calculus of CDLR of a memory hierarchy. A common metric used for the assessment of overall reliability, in a memory hierarchy is the Mean Time To Failure (MTTF), but it doesn’t take into account for the time of data storage in each level. We propose another metric, Cache Data Loss Rate (CDLR), for this reason. We will derive a recurrent formula for computing CDLR, and we will validate it by computer simulation.
Unable to display preview. Download preview PDF.
- David A. Paterson, John L. Henessy – “Computer architecture. a quantitative approach”, Morgan Kaufmann Publishers, Inc. 1990-1996.Google Scholar
- Peter M. Chen, David E. Lowell.,. Reliability hierarchies. workshop on hot topics in operating systems, 1999.Google Scholar
- Novac Ovidiu, Gordan M, Novac M., Data loss rate versus mean time to failure in memory hierarchies. Proceedings of the CISSE’05,University of Bridgeport, USA, 2005.Google Scholar
- Philip P. Shirvani and Edward J. McCluskey, “PADded cache: a new fault-tolerance technique for cache memories”, Computer Systems Laboratory, Technical Report No. 00-802, Stanford University, Stanford, California, December 2000.Google Scholar
- Miguel A. Vega-Rodríguez, “SMPCache simulator”. Available at http://arco.unex.es/smpcache.Google Scholar