In this paper we address the problems of schedule synthesis and timing verification for component-based architectures in embedded systems. We consider a component to be a set of tasks with response times that lie within specified intervals. When a set of components is deployed to implement a desired functionality, we want to guarantee that the components can achieve the timing constraints of the application. We solve the associated synthesis and verification problems using the framework of timed interface automata and timed games.
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Bhaduri, P. (2007). Schedule Verification and Synthesis for Embedded Real-Time Components. In: Ramesh, S., Sampath, P. (eds) Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6254-4_11
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DOI: https://doi.org/10.1007/978-1-4020-6254-4_11
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