As Moore’s Law continues unencumbered into the nanometer era, chips are reaching 1,000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever-increasing design complexity, and be capable of adapting to the constraints of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In this book, we present a multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization.


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© Springer 2007

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