Methodology for Heterogeneous Systems Validation

  • G. Nicolescu
  • A. A. Jerraya

The two anatomies presented in the previous chapters show that global validation of heterogeneous embedded systems requires very sophisticated execution models. These models include the execution of various components, the interpretation of the interconnects between the components as well as the adaptation of various execution models, abstractions, and communication protocols that are specific to the different components of the systems to be validated. This makes the design of these global execution models extremely challenging; it requires an increasing fraction of the overall design effort and represents a possible source of errors in this process.


Abstraction Level Module Adapter Virtual Channel Execution Model Communication Primitive 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [Bou05]
    F. Bouchhima, G. Nicolescu et al., “Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC Design”, 16th IEEE Proc. Int. Workshop on Rapid System Prototyping, June 2005.Google Scholar
  2. [Cad02]
    Cadance Design Systems, Inc., “Virtual Component Design”, available on line at
  3. [Cal97]
    J. P. Calvez, D. Heller, O. Pasquier, “Hardware/Software System Design Based on the MCSE Methodology”, Current Issues in Electronic Modeling, Vol. 9: System Design, Editors J.M. Bergé, O. Levia, J. Rouillard, Kluwer Academic Publishers, 1997, Chap. 6, pp. 115-150.Google Scholar
  4. [Cos99]
    P. Coste, F. Hessel, Ph. LeMarrec, et al., “Multilanguage Design of Heterogeneous Systems”, Proc. Int. Workshop on HardwareSoftware Codesign, May 1999.Google Scholar
  5. [Hes00]
    F. Hessel, P. Coste, G. Nicolescu, Ph. Lemarrec, et al., “Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification”, Proceedings of the IEEE International Conference On Computer Design, September 2000, Austin, USA.Google Scholar
  6. [Kea99]
    M. Keating, P. Bricaud, Reuse Methodology Manual, Kluwer Academic Publishers, 1999.Google Scholar
  7. [Kur01]
    T. Kurzweg, J. Martinez, S. Levitan, P. Marchand, D. Chairulli, “Dynamic Simulation of Optical MEM Switches”, Proc. DTIP France, April 2001.Google Scholar
  8. [Lyo01]
    D. Lyonnard, S. Yoo, A. Baghdadi, A. A. Jerraya, “Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip”, Proceedings DAC 2001, June 2001, Las Vegas, USA.Google Scholar
  9. [Mat02]
    A. Tewari, Modern Control Design with MATLAB and SIMULINK, Wiley, April 2002.Google Scholar
  10. [Mes00]
    D. J. G. Mestdagh, M.R. Isaksson, P. Odling, “Zipper VDSL: A Solution for Robust Duplex Communication over Telephone Lines”, IEEE Communication Magazine, pp. 90-96, May 2000.Google Scholar
  11. [Syn02]
    Synopsys Eaglei, available at ds.html.
  12. [Sys02]
    T. Grotker, S. Liao, G. Martin, S. Swan, System design with SystemC, Version 2.0, Springer, May 2002.Google Scholar
  13. [TIA95]
    TIA/EIA-95A, “Mobile Station-Base Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular Systems”, 1995.Google Scholar
  14. [Yoo99]
    S. Yoo, J. Lee, J. Jung, K. Rhe, Y. Cho, K. Choi, “Fast Prototyping of an IS-95 CDMA Cellular Phone : a Case Study”, Proc. 6th Conference of Asia Pacific Chip Design Languages, October 1999.Google Scholar
  15. [Wu97]
    M. C. Wu, “Micro machining for Optical and Optoelelctronic Systems”, Proc. IEEE, Vol. 85, No. 11, November 1997.Google Scholar

Copyright information

© Springer 2007

Authors and Affiliations

  • G. Nicolescu
    • 1
  • A. A. Jerraya
    • 2
  1. 1.Ecole Polytechnique de MontrealQC
  2. 2.CEA-LETIGrenoble

Personalised recommendations