Currently, the validation stage represents a bottleneck for the design flow of heterogeneous systems. This stage requires most of the design time (70–80%) [Kea99] and this is mainly because the different components of an embedded system are heterogeneous. This characteristic of current embedded systems makes very difficult the definition and implementation of global execution models enabling the global validation. These models are very complex: they guarantee the execution of different components, the interpretation of interconnections between different components and they are in charge of adaptations between different execution models and/or communication protocols. Consequently, the development of these models is a time consuming task; moreover, often it represents a source of errors during the design flow. In this context, the automatic generation of global execution models for global validation purposes becomes mandatory.
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Nicolescu, G., Jerraya, A.A. (2007). Heterogeneous Systems Validation Based on Execution Models. In: Nicolescu, G., Jerraya, A.A. (eds) Global Specification and Validation of Embedded Systems. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6153-0_4
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