System Simulation of Δ-Σ-Based Fractional-N Synthesizers
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The aim of the work presented in this monograph is the research, study, design, and implementation of high-speed Δ-Σ-based fractional synthesizers for WLAN standards (802.11a, b, and g). In chapter 3, detailed analyses of integer-N and Δ-Σ-based fractional-N phase-locked loops have been presented. Open-loop, closed loop, and phase noise equations have been derived. In this chapter, behavioral modeling for a proposed fractional-N Δ-Σ-based PLL is carried out to evaluate architectural limitations, identify dominant noise sources, automate loop filter optimization, and generate PFD/CP linearity specifications. Also, a phase-domain model of the proposed architecture is constructed using The Cadence™ Verilog-A Language. The model combines the VCO, reference, and divider integrators into one resettable integrator within the PFD. The Δ-Σ modulator model is also included. The divider adds Δ-Σ noise to the frequency variable then divides the sum by the average divide ratio. The simulation results obtained in this chapter and measured results of subblocks of the chip designed in chapter 5 contribute to the optimum design and implementation of fractional-N synthesizers presented in chapters 5 and 6.
KeywordsPhase Noise Charge Pump Loop Filter Frequency Synthesizer Loop Bandwidth
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