Phase-Locked Loop Frequency Synthesizers

Principles, Analyses, and Design
Part of the Analog Circuits and Signal Processing book series (ACSP)


In this chapter, detailed analyses of PLL frequency synthesizers are treated. Both integer and Δ-Σ-based fractional-N are considered. Open-loop and Closed-loop gain and phase equations are derived and phase noise theory is introduced. Gain and noise contributions of individual subblocks of the synthesizers are detailed. Loop filter design is also included. Together with simulations performed in chapter 4, the derived equations aid the optimum design and implementation of the two presented fractional-N synthesizer chips described in chapters 5 and 6.


Phase Noise Loop Filter Frequency Synthesizer Error Vector Magnitude Noise Power Spectrum 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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