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Clock and Data Recovery Circuit

  • Paul Muller
  • Yusuf Leblebici
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

At the output of the limiting amplifier, the amplified data signal with sharpened data edges is available for further processing, but unique interpretation of the received signal requires timing information. Serial communication links do not provide a synchronization signal on a separate channel and therefore the receiver must rely on the extraction of the timing information from the data stream. This clock and data recovery process can be performed in a similar manner in optical communication, electrical serial links, hard drive read-out channels, as well as in some memory interfaces. In the latter field, advocates and opponents of the clock forwarding scheme still debate about the advantages and drawbacks of per-channel clock recovery circuits.

Keywords

Loop Filter Clock Recovery Data Edge Recovery Circuit Random Jitter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2007

Authors and Affiliations

  • Paul Muller
    • 1
  • Yusuf Leblebici
    • 2
  1. 1.Marvell SemiconductorEtoySwitzerland
  2. 2.École Polytechnique Fédérale de LausanneLausanneSwitzerland

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