Abstract
Following the photocurrent-to-voltage conversion performed by the transimpedance amplifier, the limiting amplifier provides additional voltage gain for the signal to satisfy the input sensitivity of the attached clock and data recovery circuit. The amplitude of the CDR input signal must not only exceed this value, the rise and fall times shall also allow for accurate detection of the zero crossings. Due to the signal amplification already operated in the TIA, noise may be less critical in the limiting amplifier, although this argument loses strength in advanced CMOS receivers operating at multi-gigabit data rates, where the achievable TIA gain tends to drop below the kiloohm barrier.
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© 2007 Springer
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Muller, P., Leblebici, Y. (2007). Limiting Amplifier Design. In: CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5912-4_7
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DOI: https://doi.org/10.1007/978-1-4020-5912-4_7
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-5911-7
Online ISBN: 978-1-4020-5912-4
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