Skip to main content
SpringerLink
Log in
Book cover

Low-Frequency Noise In Advanced Mos Devices pp 103–173Cite as

1/f Noise Performance of Advanced Cmos Devices

  • Chapter

Part of the book series: Analog Circuits and Signal Processing Series ((ACSP))

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   119.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   159.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   179.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. R H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. LeBlanc, Ion implanted MOSFETs with very short channel lengths, in IEDM Tech. Dig., 1973, pp. 152-155.

    Google Scholar 

  2. R H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, Design of ion-implanted MOSFET’s with very small physical dimensions,IEEE J. Solid-State Circuits, SC-9, 256-268 (1974).

    Google Scholar 

  3. L. D. Yau, A simple theory to predict the threshold voltage of short-channel IGFETs, Solid-State Electron. 17, 1059-1063 (1974).

    Google Scholar 

  4. G Baccarani, M. R. Wordeman, and R. H. Dennard, Generalized scaling theory and its application to a 1/4 micrometer MOSFET design, IEEE Trans. Electron Devices ED-31, 452-462 (1984).

    Google Scholar 

  5. (ITRS), 2005 update, http://www.itrs.net

    Google Scholar 

  6. A. A. Abidi, RF CMOS comes of age, in Proc. Symp. VLSI Circuits, 2003, pp. 113-116.

    Google Scholar 

  7. A. A. Balandin, Noise and fluctuations control in electronic devices (American Scientific Publishers, Stevenson Ranch, CA, 2002.

    Google Scholar 

  8. C. Claeys and E. Simoen, Impact of advanced processing modules on the low-frequency noise performance of deep-submicron CMOS technologies, Microelectron. Reliab. 40, 1815-1821 (2000).

    Google Scholar 

  9. S. Okhonin, M. A. Py, B. Georgescu, H. Fischer, and L. Risch, DC and low-frequency Noise Characteristics of SiGe P-Channel FET’s Designed for 0.13-μ m Technology, IEEE Trans. Electron Devices 46, 1514-1517 (1999).

    Google Scholar 

  10. S. J. Mathew, G. Niu, W. B. Dubbelday, and J. D. Cressler, Characterization and Profile Optimization of SiGe pFET’s on Silicon-on-Sapphire, IEEE Trans. Electron Devices 46, 2323-2332 (1999).

    Google Scholar 

  11. M. J. Prest, M. J. Palmer, G. Braithwaite, T. J. Grasby, P. J. Phillips, O. A. Mironov, E. H. C. Parker, and T. E. Whall, Si/Si0.64Ge0.36/Si pMOSFETs with enhanced voltage gain and low 1/f noise, in Proc. ESSDERC, 2001, pp. 179-182.

    Google Scholar 

  12. T. Horikawa, N. Yasuda, W. Mizubayashi, K. Iwamoto, K. Tominaga, K. Akiyama, K. Yamamoto, H. Hisamatsu, H. Ota, T. Nabatame, and A. Toriumi, Low frequency noise characteristics in HfAlOx/SiO2 n-MOSFETs, in Proc. Vol. 1 Electrochem Soc. Meeting, 2004, pp. 292-303.

    Google Scholar 

  13. B. Min, S. P. Devireddy, Z. Çelik-Butler, F. Wang, A. Zlotnicka, H.-H. Tseng, and P. J. Tobin, Low-frequency noise in submicrometer MOSFETs with HfO2, HfO2/Al2O3 and HfAlOx Gate Stacks, IEEE Trans. Electron Devices 51, 1679-1687 (2004).

    Google Scholar 

  14. B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J. A. Chroboczek, P. Masson, R. Truche, A. M. Papon, F. Martin, J. F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Christoloveanu, G. Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, 75nm damascene metal gate and high-k integration for advanced CMOS devices, in IEDM Tech. Dig., 2002, pp. 355-358.

    Google Scholar 

  15. J. Chang, A. A. Abidi, and C. R. Viswanathan, Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,IEEE Trans. Electron Devices, 41, 1965-1971 (1994).

    Google Scholar 

  16. M. Fadlallah, G. Ghibaudo, J. Jomaah, M. Zoaeter, and G. Guègan, Static and low frequency noise characterization of surface- and buried-mode 0.1 μ m P and NMOSFETS, Microelectron. Reliab. 42, 41-46 (2002).

    Google Scholar 

  17. X. Li, C. Barros, E. P. Vandamme, and L. K. J. Vandamme, Parameter extraction and 1/f noise in a surface and a bulk-type, p-channel LDD MOSFET, Solid-State Electron. 37, 1853-1862 (1994).

    Google Scholar 

  18. M. Marin, M. J. Deen, M. de Murcia, P. Llinares, and J. C. Vildeuil, Effects of body biasing on the low frequency noise of MOSFETs from 130 nm CMOS technology, IEE Proc.-Circuits Devices Syst. 151, 95-101 (2004).

    Google Scholar 

  19. A. Mercha, E. Simoen, and C. Claeys, Impact of high vertical electric field on low-frequency noise in thin-gate oxide MOSFETs, IEEE Trans. Electron Devices 50, 2520-2527 (2003).

    Google Scholar 

  20. M. Valenza, A. Hoffmann, D. Sodini, A. Laigle, F. Martinez, and D. Rigaud, Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90nm, IEE Proc.-Circuits Devices Syst. 151, 102-110 (2004).

    Google Scholar 

  21. A. K. M. Ahsan and D. K. M. Schroder, Impact of post-oxidation annealing on low-frequency noise, threshold voltage, and subthreshold swing of p-channel MOSFETs, IEEE Electron Device Lett. 25, 211-213 (2004).

    Google Scholar 

  22. J-S. Lee, D. Ha, Y.-K. Choi, T.-J. King, and J. Bokor, Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate, IEEE Electron Device Lett. 24, 31-33 (2003).

    Google Scholar 

  23. Y. Nemirovsky, I. Brouk, and C. G. Jakobson, 1/f noise in CMOS transistors for analog applications, IEEE Trans. Electron Devices 48,921-927 (2001).

    Google Scholar 

  24. E. Simoen, A. Mercha, C. Claeys, and E. Young, Correlation between the 1/f noise parameters and the effective low-field mobility in HfO2 gate dielectric n-channel metal-oxide-semiconductor field-effect transistors, Appl. Phys. Lett. 85, 1057-1059 (2004).

    Google Scholar 

  25. F. Dieudonnè, S. Haendler, J. Jomaah, and F. Balestra, Low frequency noise in 0.12 μ m partially and fully depleted SOI technology, Microelectron. Reliab. 43, 243-248 (2003).

    Google Scholar 

  26. B. Min, S. P. Devireddy, and Z. Çelik-Butler, Low-frequency noise characteristics of HfSiON gate-dielectric metal-oxide-semiconductor-field-effect transistors, Appl. Phys. Lett. 86, 082102 (2005).

    Google Scholar 

  27. F. Dieudonnè, S. Haendler, J. Jomaah, and F. Balestra, Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs, Solid-State Electron. 48, 985-997 (2004).

    Google Scholar 

  28. E. Simoen, A. Mercha, C. Claeys, N. Lukyanchikova, and N. Garbar, Critical discussion of the front-back gate coupling effect on the low-frequency noise in fully depleted SOI MOSFETs, IEEE Trans. Electron Devices 51, 1008-1016 (2004).

    Google Scholar 

  29. J-S. Lee, Y.-K. Choi, D. Ha, S. Balasubramanian, T.-J. King, and J. Bokor, Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs, IEEE Electron Device Lett. 24, 186-188 (2003).

    Google Scholar 

  30. Y. Akue Allogo, M. Marin, M. de Murcia, P. Llinares, and D. Cottin, 1/f noise in 0.18 μ m technology n-MOSFETs from subthreshold to saturation, Solid-State Electron. 46, 977-983 (2002).

    Google Scholar 

  31. P. Srinivasan, E. Simoen, L. Pantisano, C. Claeys, and D. Misra, Impact of high-k gate stack material with metal gates on LF noise in n- and p-MOSFETs, Microelectron. Eng., 80, 226-229 (2005).

    Google Scholar 

  32. N. Lukyanchikova, N. Garbar, M. Petrichuk, E. Simoen, and C. Claeys, Flicker noise in deep submicron nMOS transistors, Solid-State Electron. 44, 1239-1245 (2000).

    Google Scholar 

  33. E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C. Claeys, On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors, Appl. Phys. Lett. 86, 223509, (2005).

    Google Scholar 

  34. V. Subramanian, A. Mercha, A. Dixit, K. G. Anil, M. Jurczak, K. De Meyer, S. Decoutere, H. Maes, G. Groeseneken, and W. Sansen, Geometry dependence of 1/f noise in N- and P- Channel MuGFETs, in Proc. Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 279-282.

    Google Scholar 

  35. K. W. Chew, K. S. Yeo, and S.-F. Chu, Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors, Solid-State Electron. 48, 1101-1109 (2004).

    Google Scholar 

  36. G. Giusi, F. Crupi, C. Pace, C. Ciofi, and G. Groeseneken, Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics, IEEE Trans. Electron Devices 53, 823-828 (2006).

    Google Scholar 

  37. S. P. Devireddy, B. Min, Z. Çelik-Butler, H. H. Tseng, P. J. Tobin, F. Wang, and A. Zlotnicka, Low-frequency noise in TaSiN/HfO2 nMOSFETs and the effect of stress-relieved preoxide interfacial layer, IEEE Trans. Electron Devices 53, 538-544 (2006).

    Google Scholar 

  38. P. Srinivasan, E. Simoen, R. Singanamalla, H. Y. Yu, C. Claeys, and D. Misra, Gate electrode effect on low-frequency (1/f) noise in p-MOSFETs with high-κ gate dielectrics, Solid-State Electron. 50, 992-998(2006).

    Google Scholar 

  39. F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, Impact of the interfacial layer on the low-frequency (1/f) noise behaviour of MOSFETs with advanced gate stacks, IEEE Electron Device Lett. 27, 688-691 (2006).

    Google Scholar 

  40. M. von Haartman, A.-C. Lindgren, P.-E. Hellström, B. G. Malm, S.-L. Zhang, and M. Östling, 1/f noise in Si and Si0.7Ge0.3 pMOSFETs, IEEE Trans. Electron Devices 50, 2513-2519 (2003).

    Google Scholar 

  41. M. von Haartman, B. G. Malm, and M. Östling, Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate,IEEE Trans. Electron Devices 53, 836-843 (2006).

    Google Scholar 

  42. M. von Haartman, J. Hållstedt, J. Seger, B. G. Malm, P.-E. Hellström and M. Östling, Low-frequency noise in SiGe channel pMOSFETs on ultra-thin body SOI with Ni-silicided source/drain,inProc. 18 th Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 307-310.

    Google Scholar 

  43. M. von Haartman, D. Wu, B. G. Malm, P.-E. Hellström, S.-L. Zhang and M. Östling, Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics,Solid-State Electronics 48, 2271-2275 (2004).

    Google Scholar 

  44. M. von Haartman, D. Wu, P.-E. Hellström, S.-L. Zhang and M. Östling, Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with a metal/high-κ gate stack, inProc. 17 th Int. Conf. Noise and Fluctuations (ICNF), 2003, pp. 381-384.

    Google Scholar 

  45. M. von Haartman, B. G. Malm, P.-E. Hellström and M. Östling, Noise in Si and SiGe MOSFETs with high-k gate dielectrics, inProc. 18 th Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 225-230.

    Google Scholar 

  46. M. von Haartman, Ph. D. Thesis, KTH, Royal Institute of Technology, Sweden, 2006.

    Google Scholar 

  47. G. Ghibaudo, and T. Boutchacha, Electrical noise and RTS fluctuations in advanced CMOS devices, Microelectron. Reliab. 42, 573-582 (2002).

    Google Scholar 

  48. R. Brederlow, W. Weber, D. Schmitt-Landsiedel, and R. Thewes, Fluctuations of the low frequency noise of MOS transistors and their modeling in analog and RF-circuits, in IEDM Tech. Dig., 1999, pp. 159-162.

    Google Scholar 

  49. M. Sandèn, O. Marinov, M. J. Deen, and M. Östling, A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs, IEEE Trans. Electron Devices 49, 514-520 (2002).

    Google Scholar 

  50. J. Brini, G. Ghibaudo, G. Kamarinos, and O. Roux-dit-Buisson, Scaling down and low-frequency noise in MOSFET’s: are the RTS’s the ultimate components of the 1/f noise?, AIP Conf. Proc. 282, 31-48 (1993).

    Article  Google Scholar 

  51. C. Claeys, A. Mercha, and E. Simoen, Low-frequency noise assessment for deep submicrometer CMOS technology nodes,J. Electrochem. Soc. 151, G307-G318 (2004).

    Google Scholar 

  52. L. K. J. Vandamme, X. Li, and D. Rigaud, 1/f noise in MOS devices, mobility or number fluctuations?, IEEE Trans. Electron Devices 41, 1936-1945 (1994).

    Google Scholar 

  53. A. van der Ziel, Noise in solid state devices and circuits (John Wiley & Sons, New York, 1986).

    Google Scholar 

  54. M. Bhat, D. J. Wristers, L.-K. Han, J. Yan, H. J. Fulford, and D.-L. Kwong, Electrical properties and reliability of MOSFET’s with rapid thermal NO-nitrided SiO2 gate dielectrics,IEEE Trans. Electron Devices, 42, 907-914 (1995).

    Google Scholar 

  55. M. A. Schmidt, F. L. Terry, Jr., B. P. Mathur, and S. D. Senturia, Inversion layer mobility of MOSFET’s with nitrided oxide gate dielectrics, IEEE Trans. Electron Devices, 35, 1627-1632 (1988).

    Google Scholar 

  56. T. Ishihara, K. Matsuzawa, M. Takayanagi, and S. Takagi, Comprehensive understanding of electron and hole mobility limited by surface roughness scattering in pure oxides and oxynitrides based on correlation function of surface roughness, Jpn. J. Appl. Phys. 41, 2353-2358 (2002).

    Google Scholar 

  57. P. Morfouli, G. Ghibaudo, T. Ouisse, E. Vogel, W. Hill, V. Misra, P. McLarty, and J. J. Wortman, Low-frequency noise characterization of n- and p-MOSFET’s with ultrathin oxynitride gate films, IEEE Electron Device Lett. 17, 395-397 (1996).

    Google Scholar 

  58. M. Da Rold, E. Simoen, S. Mertens, M. Schaekers, G. Badenes, and S. Decoutere, Impact of gate oxide nitridation process on 1/f noise in 0.18 μ m CMOS, Microelectron. Reliab. 41, 1933-1938 (2001).

    Google Scholar 

  59. M. Marin, J. C. Vildeuil, B. Tavel, B. Duriez, F. Arnaud, P. Stolk, and M. Woo, Can 1/f noise in MOSFETs be reduced by gate oxide and channel optimization?, in Proc. Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 195-198.

    Google Scholar 

  60. T. Contaret, K. Romanjek, T. Boutchacha, G. Ghibaudo, and F. Bœuf, Low frequency noise characterization and modelling in ultrathin oxide MOSFETs, Solid-State Electron. 50, 63-68 (2006).

    Google Scholar 

  61. J. Lee and G. Bosman, Comprehensive noise performance of ultrathin oxide MOSFETs at low frequencies, Solid-State Electron. 48, 61-71 (2004).

    Google Scholar 

  62. J. Lee and G. Bosman, Defect spectroscopy using 1/f γ noise of gate leakage current in ultrathin oxide MOSFETs, Solid-State Electron. 47, 1973-1981 (2003).

    Google Scholar 

  63. J. Lee, G. Bosman, K. R. Green, and D. Ladwig, Model and analysis of gate leakage current in ultrathin nitrided oxide MOSFETs, IEEE Trans. Electron Devices 49, 1232-1241 (2002).

    Google Scholar 

  64. J. Lee, G. Bosman, K. R. Green, and D. Ladwig, Noise model of gate-leakage current in ultrathin oxide MOSFETs, IEEE Trans. Electron Devices 50, 2499-2506 (2003).

    Google Scholar 

  65. R. People, Physics and applications of GexSi1 - x/Si strained-layer heterostructures, IEEE J. Quantum Electronics QE-22, 1696-1710 (1986).

    Google Scholar 

  66. D. J. Robbins, L. T. Canham, S. J. Barnett, A. D. Pitt, and P. Calcott, Near-band-gap photoluminescence from pseudomorphic Si1 - xGex single layers on silicon, J. Appl. Phys. 71, 1407-1414 (1992).

    Google Scholar 

  67. T. Manku, J. M. McGregor, A. Nathan, D. J. Roulston, J.-P. Noel, and D. C. Houghton, Drift hole mobility in strained and unstrained doped Si1 - xGex alloys,IEEE Trans. Electron Devices 40, 1990-1996 (1993).

    Google Scholar 

  68. T. Manku and A. Nathan, Effective mass for strained p-type Si1 - xGex, J. Appl. Phys. 69, 8414-8416 (1991).

    Google Scholar 

  69. S. Verdonckt-Vandebroek, E. F. Crabbè, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, and J. B. Johnson, SiGe-Channel Heterojunction p-MOSFET’s, IEEE Trans. Electron Devices,41, 90-101 (1994).

    Google Scholar 

  70. C-G. Ahn, H.-S. Kang, Y.-K. Kwon, and B. Kang, Effects of segregated Ge on electrical properties of SiO2/SiGe interface, Jpn. J. Appl. Phys., 37, 1316-1319 (1998).

    Google Scholar 

  71. T. Ngai, X. Chen, J. Chen, and S. K. Banerjee, Improving SiO2/SiGe interface of SiGe p-metal-oxide-semiconductor field-effect transistors using water vapor annealing, Appl. Phys. Lett. 80, 1773-1775 (2002).

    Google Scholar 

  72. M. von Haartman, A.-C. Lindgren, P.-E. Hellström, M. Östling, T. Ernst, L. Brèvard and S. Deleonibus, Influence of gate width on 50 nm gate length Si0.7Ge0.3 channel PMOSFETs, in Proc. 33 rd ESSDERC, 2003, pp. 529-532.

    Google Scholar 

  73. N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology, Solid-State Electron. 47, 1173-1177 (2003).

    Google Scholar 

  74. F. Andrieu, T. Ernst, K. Romanjek, O. Weber, C. Renard, J.-M. Hartmann, A. Toffoli, A.-M. Papon, R. Truche, P. Holliger, L. Brèvard, G. Ghibaudo, and S. Deleonibus, SiGe channel p-MOSFETs scaling-down, in Proc. ESSDERC, 2003, pp. 267-270.

    Google Scholar 

  75. K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, Characterization of the effective mobility by split C(V) technique in sub 0.1 μ m Si and SiGe PMOSFETs, Solid-State Electron. 49, 721-726 (2005).

    Google Scholar 

  76. A-C. Lindgren, P.-E. Hellberg, M. von Haartman, D. Wu, C. Menon, S.-L. Zhang, and M. Östling, Enhanced intrinsic gain (gm/gd) of PMOSFETs with a Si0.7Ge0.3 channel, in Proc. ESSDERC, 2002, pp. 175-178.

    Google Scholar 

  77. J. Alieu, T. Skotnicki, E. Josse, J.-L. Regolini, and G. Bremond, Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances, in Proc. Symp. VLSI Techology, 2000, pp. 130-131.

    Google Scholar 

  78. Y-C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C. Hu, Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel, IEEE Trans. Electron Devices, 49, 279-286 (2002).

    Google Scholar 

  79. T. Tsuchiya, T. Matsuura, and J. Murota, Low-Frequency Noise in Si1 - xGex p-Channel Metal Oxide Semiconductor Field-Effect Transistors, Jpn. J. Appl. Phys. Part I 40, 5290-5293 (2001).

    Google Scholar 

  80. P. W. Li, W. M. Liao, C. C. Shih, T. S. Kuo, L. S. Lai, Y. T. Tseng, and M. J. Tsai, High performance Si/SiGe heterostructure MOSFETs for low power analog circuit applications, Solid-State Electron. 47, 1095-1098 (2003).

    Google Scholar 

  81. G. Ghibaudo and J. Chroboczek, On the origin of the LF noise in Si/Ge MOSFETs, Solid-State Electron. 46, 393-398 (2002).

    Google Scholar 

  82. M. J. Prest, A. R. Bacon, D. J. F. Fulgoni, T. J. Grasby, E. H. C. Parker, T. E. Whall, and A. M. Waite, Low-frequency noise mechanisms in Si and pseudomorphic SiGe p-channel field-effect transistors, Appl. Phys. Lett. 85, 6019-6021 (2004).

    Google Scholar 

  83. M. Myronov, O. A. Mironov, S. Durov, T. E. Whall, E. H. C. Parker, T. Hackbarth, G. Höck, H.-J. Herzog, and U. König, Reduced 1/f noise in p-Si0.3Ge0.7 metamorphic metal-oxide-semiconductor field-effect transistor, Appl. Phys. Lett. 84, 610-612 (2004).

    Google Scholar 

  84. P. Srinivasan, E. Simoen, B. De Jaeger, C. Claeys, and D. Misra, 1/f noise performance of MOSFETs with HfO2 and metal gate on Ge-on-insulator substrates, Mat. Sci. Sem. Proc. in press (2006).

    Google Scholar 

  85. M. V. Fischetti and S. E. Laux, Band structure, deformation potentials, and carrier mobility in strained Si, Ge and SiGe alloys, J. Appl. Phys. 80, 2234-2252 (1996).

    Google Scholar 

  86. S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, A 90-nm logic technology featuring strained-silicon, IEEE Trans. Electron Devices 51, 1790-1797 (2004).

    Google Scholar 

  87. J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, Strained silicon MOSFET technology, inIEDM Tech. Dig., 2002, pp. 23-26.

    Google Scholar 

  88. S. H. Olsen, K. S. K. Kwa, L. S. Driscoll, S. Chattopadhyay, and A. G. O’Neill, Design, fabrication and characterisation of strained Si/SiGe MOS transistors, IEE Proc.-Circuits Devices Syst. 151, 431-437 (2004).

    Google Scholar 

  89. T. Tezuka, N. Sugiyama, and S. Takagi, Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction, Appl. Phys. Lett. 79, 1798-1800 (2001).

    Google Scholar 

  90. M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, Six-band k.p calculation of the hole mobility in silicon inversion layers: dependence on surface orientation, strain, and silicon thickness, J. Appl. Phys. 94, 1079-1095 (2003).

    Google Scholar 

  91. M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D’Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, High performance CMOS fabricated on hybrid substrate with different crystal orientations, inIEDM Tech. Dig., 2003, pp. 453-456.

    Google Scholar 

  92. T. Komoda, A. Oishi, T. Sanuki, K. Kasai, H. Yoshimura, K. Ohno, M. Iwai, M. Saito, F. Matsuoka, N. Nagashima, and T. Noguchi, Mobility improvement for 45 nm node by combination of optimized stress control and channel orientation design, in IEDM Tech. Dig., 2004, pp. 217-220.

    Google Scholar 

  93. K. Rim, J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K .Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J .Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs, in Proc. Symp. VLSI Technology, 2002, pp. 98-99.

    Google Scholar 

  94. F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Boeuf, and T. Skotnicki, Low temperature characterization of effective mobility in uniaxially and biaxially strained nMOSFETs,Solid-State Electron. 50, 644-649 (2006).

    Google Scholar 

  95. J-S. Goo, Q. Xiang, Y. Takamura, H. Wang; J. Pan, F. Arasnia, E. N. Paton, P. Besser, M. V. Sidorov, E. Adem, A. Lochtefeld, G. Braithwaite, M .T. Currie, R. Hammond, M. T. Bulsara, and M.-R. Lin, Scalability of strained-Si nMOSFETs down to 25 nm gate length, IEEE Electron Device Letters 24, 351-353 (2003).

    Google Scholar 

  96. T. Ohguro, Y. Okayama, K. Matsuzawa, K. Matsunaga, N. Aoki, K. Kojima, H. S. Momose, and K. Ishimaru, The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11 μ m CMOS, in Proc. Symp. VLSI Technology, 2003, pp. 37-38.

    Google Scholar 

  97. G. Giusi, E. Simoen, G. Eneman, P. Verheyen, F. Crupi, K. De Meyer, C. Claeys, and C. Ciofi, Low-frequency (1/f) noise behavior of locally stressed HfO2/TiN gate-stack pMOSFETs, IEEE Electron Device Lett. 27, 508-510 (2006).

    Google Scholar 

  98. M. H. Lee, P. S. Chen, W.-C. Hua, C.-Y. Yu, Y. T. Tseng, S. Maikap, Y. M. Hsu, C. W. Liu, S. C. Lu, W.-Y. Hsieh, and M.-J. Tsai, Comprehensive low-frequency and RF noise characteristics in strained-Si NMOSFETs, in IEDM Tech. Dig., 2003, pp. 69-72.

    Google Scholar 

  99. W-C. Hua, M. H. Lee, L. P. S. Chen, S. Maikap, C. W. Liu, and K. M. Chen, Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs, IEEE Electron Device Lett. 25, 693-695 (2004).

    Google Scholar 

  100. W-C. Hua, M. H. Lee, P. S. Chen, M.-J. Tsai, and C. W. Liu, Threading dislocation induced low frequency noise in strained-Si nMOSFETs, IEEE Electron Device Lett. 26, 667-669 (2005).

    Google Scholar 

  101. E Simoen, G. Eneman, P. Verheyen, R. Loo, K. De Meyer, and C. Claeys, Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates, IEEE Trans. Electron Devices 53, 1039-1047 (2006).

    Google Scholar 

  102. J-P. Colinge, Fully-depleted SOI CMOS for analog applications, IEEE Trans. Electron Devices 45, 1010-1016 (1998).

    Google Scholar 

  103. S Cristoloveanu, Silicon on insulator technologies and devices: from present to future, Solid-State Electron. 45, 1403-1411 (2001).

    Google Scholar 

  104. T Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, Ultimately thin double-gate SOI MOSFETs,IEEE Trans. Electron Devices 50, 830-838 (2003).

    Google Scholar 

  105. S Narasimha, A. Ajmera, H. Park, D. Schepis, N. Zamdmer, K. A. Jenkins, J.-O. Plouchart, W.-H. Lee, J. Mezzapelle, J. Bruley, B. Doris, J. W. Sleight, S. K. Fung, S. H. Ku, A. C. Mocuta, I. Yang, P. V. Gilbert, K. P. Muller, P. Agnello, and J. Welser, High performance sub-40nm CMOS devices on SOI for the 70nm technology node, in IEDM Tech. Dig., 2001, pp. 625-628.

    Google Scholar 

  106. S Monfray, T. Skotnicki, C. Fenouillet-Beranger, N. Carriere, D. Chanemougame, Y. Morand, S. Descombes, A. Talbot, D. Dutartre, C. Jenny, P. Mazoyer, R. Palla, F. Leverd, Y. Le Friec, R. Pantel, S. Borel, D. Louis, and N. Buffet, Emerging silicon-on-nothing (SON) devices technology, Solid-State Electron. 48, 887-895 (2004).

    Google Scholar 

  107. B .Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F.-F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S. P. Wong, and W. Haensch, Extreme scaling with ultra-thin Si channel MOSFETs, inIEDM Tech. Dig., 2002, pp. 267-270.

    Google Scholar 

  108. M Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. J. Auberton-Herve, J. M. Lamure, T. Barge, F. Metral, and S. Trucchi, ‘Smart cut’: a promising new SOI material technology, in Proc. IEEE Int. SOI Conf., 1995, pp. 178-179.

    Google Scholar 

  109. C Claeys, E. Simoen, A. Efremov, V. G. Litovchenko, A. Evtukh, A. Kizjak, and Ju. Rassamakin, γ -irridation hardness of short-channel nMOSFETs fabricated in a 0.5 μ m SOI technology, Nucl. Instr. and Meth. B 186, 429-434 (2002).

    Google Scholar 

  110. A Mercha, E. Simoen, H. van Meer, and C. Claeys, Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal-oxide-semiconductor field-effect-transistors, Appl. Phys. Lett. 82, 1790-1792 (2003).

    Google Scholar 

  111. F-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Yeo, M.-S. Liang, and C. Hu, 25 nm CMOS Omega FETs, in IEDM Tech. Dig., 2002, pp. 255-258.

    Google Scholar 

  112. J-P. Colinge, Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFET’s, IEEE Trans. Electron Devices 37, 718-723 (1990).

    Google Scholar 

  113. E Simoen, and C. Claeys, The low-frequency noise behaviour of silicon-on-insulator technologies, Solid-State Electron. 39, 949-960 (1996).

    Google Scholar 

  114. M Matloubian, F. Scholz, and L. Lum, Low frequency noise in fully depleted SOI PMOSFET’s, IEEE Trans. Electron Devices 41, 1977-1980 (1994).

    Google Scholar 

  115. N Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, and C. Claeys, Back and front interface related generation-recombination noise in buried-channel SOI pMOSFETs, IEEE Trans. Electron Devices 43, 417-423 (1996).

    Google Scholar 

  116. F Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance, IEEE Electron. Device Lett. EDL-8, 410-412 (1987).

    Google Scholar 

  117. Y-C. Tseng, W. M. Huang, M. Mendicino, D. J. Monk, P. J. Welch, and J. C. S. Woo, Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs, IEEE Trans. Electron Devices, 48, 1428-1437 (2001).

    Google Scholar 

  118. Web-based simulation tool, http://www.nanohub.org

    Google Scholar 

  119. J Hållstedt, M. von Haartman, P.-E. Hellström, M. Östling and H. H. Radamson, Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels, IEEE Electron Device Lett 27, 466-468, 2006.

    Google Scholar 

  120. M Fritze, C. L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast, J. Snyder, and J. Larson, High-speed schottky-barrier pMOSFET with fT = 280 GHz, IEEE Electron Device Lett. 25, 220-222 (2004).

    Google Scholar 

  121. J Seger, P.-E. Hellström, J. Lu, B. G. Malm, M. von Haartman, M. Östling, and S.-L. Zhang, Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator, Appl. Phys. Lett. 86, 253507 (2005).

    Google Scholar 

  122. K M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, BSIM4 gate leakage model including source-drain partition, in IEDM Tech. Dig., 2000, pp. 815-818.

    Google Scholar 

  123. G D. Wilk, R. M. Wallace, and J. M. Anthony, High-κ gate dielectrics: Current status and materials properties considerations, J. Appl. Phys. 89, 5243-5275 (2001).

    Google Scholar 

  124. E P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okron-Schmidt, C. D’Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-Å. Ragnarsson, P. Ronsheim, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, Ultrathin high-K gate stacks for advanced CMOS devices, in IEDM Tech. Dig., 2001, pp. 451-454.

    Google Scholar 

  125. A L. P. Rotondaro, M. R. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. T. Laaksonen, L. Tsung, M. Douglas, R. Kuan, M. J. Bevan, T. Grider, J. McPherson, and L. Colombo, Advanced CMOS transistors with a novel HfSiON gate dielectric, in Proc. Symp. VLSI Technology, 2002, pp. 148-149.

    Google Scholar 

  126. W J. Zhu and T. P. Ma, Temperature Dependence of channel mobility in HfO2-gated NMOSFETs, IEEE Electron Device Lett 25, 89-91 (2004).

    Google Scholar 

  127. S Saito, D. Hisamoto, S. Kimura, and M. Hiratani, Unified mobility model for high-κ gate stacks, in IEDM Tech. Dig., 2003, pp.797-800.

    Google Scholar 

  128. Z Ren, M. V. Fischetti, E. P. Gusev, E. A. Cartier, and M. Chudzik, Inversion channel mobility in high-κ high performance MOSFETs, in IEDM Tech Dig., 2003, pp. 793-796.

    Google Scholar 

  129. L-Å. Ragnarsson, L. Pantisano, V. Kaushik, S.-I. Saito, Y. Shimamoto, S. De Gendt, and M. Heyns, The impact of sub monolayers of HfO2 on the device performance of high-k based transistors, in IEDM Tech. Dig., 2003, pp. 87-90.

    Google Scholar 

  130. G-W. Lee, J.-H. Lee, H.-W. Lee, M.-K. Park, D.-G. Kang, and H.-K. Youn, Trap evolutions of metal/oxide/silicon field-effect transistors with high-k gate dielectric using charge pumping method, Appl. Phys. Lett. 81, 2050-2052 (2002).

    Google Scholar 

  131. J Robertson, Interfaces and defects of high-K oxides on silicon, Solid-State Electron. 49, 283-293 (2005).

    Google Scholar 

  132. M Fadlallah, A. Szewczyk, C. Giannakopoulos, B. Cretu, F. Monsieur, T. Devoivre, J. Jomaah, and G. Ghibaudo, Low-frequency noise and reliability properties of 0.12 μ m CMOS devices with Ta2O5 as gate dielectrics, Microelectron. Reliab. 41, 1361-1366, (2001).

    Google Scholar 

  133. T Ishikawa, S. Tsujikawa, S. Saito, D. Hisamoto, and S. Kimura, Direct evaluation of an interfacial layer in high-κ gate dielectrics by 1/f noise measurements, in Proc. Int. Conf. Solid State Devices and Materials (SSDM), 2003, pp. 14-15.

    Google Scholar 

  134. E Simoen, A. Mercha, L. Pantisano, C. Claeys, and E. Young, Low-frequency noise study of n-MOSFETs with HfO2 gate dielectric, in Proc. Vol. 22 Electrochem Soc. Meeting, 2003, pp. 319-331.

    Google Scholar 

  135. H Sauddin, Y. Yoshihara, S. Ohmi, K. Tsutsui, and H. Iwai, Low-frequency noise characteristics of MISFETs with La2O3 gate dielectrics, in Proc. Vol. 22 Electrochem Soc. Meeting, 2003, pp. 415-423.

    Google Scholar 

  136. H D. Xiong, D. M. Fleetwood, J. A. Felix, E. P. Gusev, and C. D’Emic, Low-frequency noise and radiation response of metal-oxide-semiconductor transistors with Al2O3/SiOxNy/Si(100) gate stacks, Appl. Phys. Lett. 83, 5232-5234 (2003).

    Google Scholar 

  137. E Simoen, A. Mercha, L. Pantisano, C. Claeys, and E. Young, Low-frequency noise behavior of SiO2-HfO2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness, IEEE Trans. Electron Devices 51, 780-784 (2004).

    Google Scholar 

  138. A Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics,IEEE Electron Device Lett. 24, 87-89 (2003).

    Google Scholar 

  139. S Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,J. Appl. Phys. 93, 9298-9303 (2003).

    Google Scholar 

  140. J S. Cable, R. A. Mann, and J. C. S. Woo, Impurity barrier properties of reoxidized nitrided oxide films for use with P+-doped polysilicon gates, IEEE Electron Device Lett., 12, 128-130 (1991).

    Google Scholar 

  141. C Claeys, E. Simoen, A. Mercha, L. Pantisano, and E. Young, Low-frequency noise performance of HfO2-based gate stacks, J. Electrochem. Soc. 152, F115-F123 (2005).

    Google Scholar 

  142. D Wu, A.-C. Lindgren, S. Persson, G. Sjöblom, M. von Haartman, J. Seger, P.-E. Hellström, J. Olsson, H.-O. Blom, S.-L. Zhang, M. Östling, E. Vainonen-Ahlgren, W.-M. Li, E. Tois, and M. Tuominen, A novel strained Si0.7Ge0.3surface-channel pMOSFET with an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack, IEEE Electron Device Lett. 24, 171-173 (2003).

    Google Scholar 

  143. M V. Fischetti, D. A. Neumayer, and E. A. Cartier, Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering, J. Appl. Phys. 90, 4587-4608 (2001).

    Google Scholar 

  144. E Simoen, A. Mercha, L. Pantisano, C. Claeys, and E. Young, Tunneling 1/fγ noise in 5 nm HfO2/2.1 nm SiO2 gate stack n-MOSFETs, Solid-State Electron. 49, 702-707 (2005).

    Google Scholar 

  145. C Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, Characterization and modelling of hysteresis phenomena in high k dielectrics, in IEDM Tech. Dig., 2004, pp. 737-740.

    Google Scholar 

  146. H..Yu, Y.-T. Hou, M.-F. Li, and D.-L. Kwong, Investigation of hole-tunneling current through ultrathin oxynitride/oxide stack gate dielectrics in p-MOSFETs, IEEE Trans. Electron Devices 49, 1158-1164 (2002).

    Google Scholar 

  147. H-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramòn, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I. Hedge, R. Noble, M. Jahanbani, C. El-Chemali, and B.White, Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO2stack, in IEDM Tech. Dig., 2004, pp. 821-824.

    Google Scholar 

  148. B Min, S. P. Devireddy, Z. Çelik-Butler, A. Shanware, L. Colombo, K. Green, J. J. Chambers, M. R. Visokay, and A. L. P. Rotondaro, Impact of interfacial layer on Low-frequency noise of HfSiON dielectric MOSFETs, IEEE Trans. Electron Devices 53, 1459-1466 (2006).

    Google Scholar 

  149. M Sandèn, B. Gunnar Malm, J. V. Grahn, and M. Östling, Decreased low-frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors, Microelectron. Reliab. 40, 1863-1867 (2000).

    Google Scholar 

  150. P Srinivasan, E. Simoen, Z. M. Rittersma, W. Deweerd, L. Pantisano, C. Claeys, and D. Misra, Effect of nitridation on low-frequency (1/f) noise in n- and p-MOSFETs with HfO2 gate dielectrics, J. Electrochem. Soc. 153, G819-G825 (2006).

    Google Scholar 

  151. M von Haartman, J. Westlinder, D. Wu, B. G. Malm, P.-E. Hellström, J. Olsson and M. Östling, Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics, Solid-State Electronics 49, 907-914 (2005).

    Google Scholar 

  152. P Xuan and J. Bokor, Investigation of NiSi and TiSi as CMOS gate materials, IEEE Electron Device Lett. 24, 634-636 (2003).

    Google Scholar 

  153. G Sjöblom, J. Westlinder, and J. Olsson, Investigation of the thermal stability of reactively sputter deposited TiN MOS gate electrodes,IEEE Trans. Electron Devices 52, 2349-2352 (2005).

    Google Scholar 

  154. R Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, High-κ /metal-gate stack and its MOSFETs characteristics, IEEE Electron Device Lett. 25, 408-410 (2004).

    Google Scholar 

  155. P Srinivasan, E. Simoen, L. Pantisano, C. Claeys, and D. Misra, Impact of gate material on low-frequency noise of nMOSFETs with 1.5 nm SiON gate dielectric: testing the limits of the number fluctuation theory, in Proc. Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 231-234.

    Google Scholar 

  156. D Esseni, M. Mastrapasqua, C. Fiegna, G. K. Keller, L. Selmi, and E. Sangiorgi, An experimental study of low-field electron mobility in double-gate ultra-thin SOI MOSFETs, in IEDM Tech. Dig., 2001, pp. 445-448.

    Google Scholar 

  157. E Simoen, U. Magnusson, and C. Claeys, A low-frequency noise study of gate-all-around SOI transistors, IEEE Trans. Electron Devices 40, 2054-2059 (1993).

    Google Scholar 

  158. B Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, FinFET scaling to 10nm gate length, inIEDM Tech. Dig., 2002, pp. 251-254.

    Google Scholar 

  159. D Esseni, A. Abramo, L. Selmi, and E. Sangiorgi, Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI nMOSFETs,IEEE Trans. Electron Devices 50, 2445-2455 (2003).

    Google Scholar 

  160. P Gaubert, A. Teramoto, T. Hamada, M. Yamamoto, K. Kotani, and T. Ohmi, 1/f noise suppression of pMOSFETs fabricated on Si(110) and Si(100) using an alkali-free cleaning process,IEEE Trans. Electron Devices 53, 851-856, 2006.

    Google Scholar 

  161. H S. Momose, T. Ohguro, K. Kojima, S.-I. Nakamura, and Y. Toyoshima, 1.5-nm gate oxide CMOS on (110) surface-oriented Si substrate, IEEE Trans. Electron Devices 50, 1001-1008 (2003).

    Google Scholar 

  162. J-S. Lee, Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, Low-frequency noise characteristics in p-channel FinFETs,IEEE Electron Device Lett. 23, 722-724 (2002).

    Google Scholar 

  163. K Akarvardar, B. M. Dufrene, S. Cristoloveanu, P. Gentil, B. J. Blalock, and M. M. Mojarradi, Low-frequency noise in SOI four-gate transistors, IEEE Trans. Electron Devices 53, 829-835 (2006).

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. KTH, Royal Institute of Technology, School of Information and Communication Technology, Kista, Sweden

    Martin von Haartman & Mikael Östling

Authors
  1. Martin von Haartman
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Mikael Östling
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2007 Springer

About this chapter

Cite this chapter

Haartman, M.v., Östling, M. (2007). 1/f Noise Performance of Advanced Cmos Devices. In: Low-Frequency Noise In Advanced Mos Devices. Analog Circuits and Signal Processing Series. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5910-0_4

Download citation

  • DOI: https://doi.org/10.1007/978-1-4020-5910-0_4

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-1-4020-5909-4

  • Online ISBN: 978-1-4020-5910-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation