Advertisement

Basics of Reconfigurable Computing

  • Reiner Hartenstein
  • Tu Kaiserslautern

This chapter introduces the basic concepts of Reconfigurable Computing and its disruptive impact on the classical instruction-streambased mind set of computing sciences. It illustrates the essentials of the paradigm shift by Reconfigurable Computing and explains the mechanisms behind the massive speed-ups obtained by software to configware migration.

Keywords

Data Stream Embed System Systolic Array Program Counter Pipe Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    A. Burks, H. Goldstein, J. von Neumann: Preliminary discussion of the logical design of an electronic computing instrument; US Army Ord-nance Department Report, 1946Google Scholar
  2. [2]
    H. Goldstein, J. von Neumann, A. Burks: Report on the mathematical and logical aspects of an electronic computing instrument; Princeton IAS, 1947Google Scholar
  3. [3]
    M. J. Smith: Application Specific Integrated Circuits; Addison Wesley, 1997Google Scholar
  4. [4]
    R. Hartenstein (invited): The Microprocessor Is No more General Pur-pose; Proceedings of IEEE International Symposium on Innovative Sys-tems (ISIS), October 9-11, 1997, Austin, TexasGoogle Scholar
  5. [5]
    L. Rizzatti: Is there any future for ASIC emulators? (or How FPGA-Based Prototypes Can Replace ASIC Emulators); EDA Alert e-Newsletter PlanetEE, February 18, 2003, www.planetee.com
  6. [6]
    T. Makimoto (keynote): The Rising Wave of Field-Programmability; FPL 2000, Villach, Austria, August 27-30, 2000; Springer Verlag, Heidelberg/New York, 2000Google Scholar
  7. [7]
    J. Becker(invited tutorial): Reconfigurable Computing Systems;Proceedings Escola de Microeletr ônica da SBC - Sul (EMICRO 2003), Rio Grande, Brasil, September 2003Google Scholar
  8. [8]
    J. Becker, S. Vernalde (editors): Advances in Reconfigurable Archi-tectures - Part 1; special issue, International Journal on Embedded Systems, 2006Google Scholar
  9. [9]
    J. Becker, S. Vernalde (editors): Advances in Reconfigurable Archi-tectures - Part 2; special issue, International Journal on Embedded Systems, 2006Google Scholar
  10. [10]
    F. Faggin, M. Hoff, S. Mazor, M. Shima: The history of 4004; IEEE Micro, December 1996Google Scholar
  11. [11]
    R. Hartenstein (invited talk): Reconfigurable supercomputing: What are the Problems? What are the Solutions? Seminar on Dynamically Recon-figurable Architectures, Dagstuhl Castle, Wadern, Germany, April 2-7, 2006Google Scholar
  12. [12]
    R. Hartenstein (opening keynote): From Organic Computing to Recon-figurable Computing; 8th Workshop on Parallel Systems and Algorithms (PASA 2006), March 16, 2006, Frankfurt/Main, Germany - in conjunction with the 19th International Conference on Architecture of Computing Systems (ARCS 2006), March 13-16, 2006, Frankfurt/Main, GermanGoogle Scholar
  13. [13]
    R. Hartenstein (opening keynote): Supercomputing goes reconfigurable-About key issues and their impact on CS education; Winter International Symposium on Information and Communication Technologies (WISICT 2005), Cape Town, South Africa, January 3-6, 2005Google Scholar
  14. [14]
    R. Hartenstein (plenum keynote address): Software or Configware? About the Digital Divide of Computing; 18th International Parallel and Distributed Processing Symposium (IPDPS), April 26-30, 2004, Santa Fe, New Mexico, USAGoogle Scholar
  15. [15]
    R. Hartenstein (invited presentation): The Digital Divide of Computing; 2004 ACM International Conference on Computing Frontiers (CF04); April 14-18, 2004, Ischia, ItalyGoogle Scholar
  16. [16]
    R. Hartenstein (invited keynote address): The Impact of Morphware on Parallel Computing; 12th Euromicro Conference on Parallel, Distributed and Network based Processing (PDP04); February 11-13, 2004, A Coru ña, SpainGoogle Scholar
  17. [17]
    D. Chinnery, K. Keutzer: Closing the Gap between ASIC & Custom; Kluwer 2002Google Scholar
  18. [18]
    A. Grove: Only the Paranoid Survive; Currence 1996Google Scholar
  19. [19]
    A.A. Gaffar, W. Luk: Accelerating Radiosity Calculations; FCCM 2002Google Scholar
  20. [20]
    M. Gokhale et al.: Acceleration of Traffic Simulation on Reconfigurable Hardware; 2004 MAPLD International Conference, September 8-10, 2004, Washington, D.C, USAGoogle Scholar
  21. [21]
    F. Dittrich: World’s Fastest Lanman/NTLM Key Recovery Server Shipped; Picocomputing, 2006 URL:[22]Google Scholar
  22. [22]
  23. [23]
    K. Gaj, T. El-Ghazawi; Cryptographic Applications; RSSI Recon-figurable Systems Summer Institute, July11-13,2005, Urbana-Champaign, IL, USA URL: [24]Google Scholar
  24. [24]
  25. [25]
    J. Hammes, D. Poznanovic: Application Development on the SRC Com-puters, Inc. Systems; RSSI Reconfigurable Systems Summer Institute, July 11-13, 2005, Urbana-Champaign, IL, USAGoogle Scholar
  26. [26]
    ASM = Auto-Sequencing Memory; DSP = Digital Signal Processing; EDA = Electronics Design Automation; ESL = Electronic System-Level Design; FIR = Finite Impulse Response; FPGA = Field-Programmable Gate-Array; MAC = Multiply and Accumulate; PU = Processing Unit rDPA = reconfigurable Data Path Array; rDPU = reconfigurable Data Path Unit; rE = reconfigurable ElementGoogle Scholar
  27. [27]
    W. Roelandts (keynote): FPGAs and the Era of Field Programmability; International Conference on Field Programmable Logic and Applications (FPL), August 29-September 1, 2004, Antwerp, Belgium,Google Scholar
  28. [28]
    J. Rabaey: Reconfigurable Processing: The Solution to Low-Power Pro-grammable DSP; ICASSP 1997Google Scholar
  29. [29]
    Y. Gu et al.: FPGA Acceleration of Molecular Dynamics Computations;FCCM 2004 URL: [30]Google Scholar
  30. [30]
  31. [31]
    A. Alex, J. Rose et al.: Hardware Accelerated Novel Protein Identifica-tion; FPL 2004Google Scholar
  32. [32]
    N.N. Nallatech, press release, 2005Google Scholar
  33. [33]
    H. Singpiel, C. Jacobi: Exploring the Benefits of FPGA-Processor Tech-nology for Genome Analysis at Acconovis; ISC 2003, June 2003, Heidelberg, Germany URL. [34]Google Scholar
  34. [34]
  35. [35]
    N.N. (Starbridge): Smith-Waterman pattern matching; National Cancer Institute, 2004Google Scholar
  36. [36]
    A. Darabiha: Video-Rate Stereo Vision on Reconfigurable Hardware; Master Thesis, University of Toronto, 2003Google Scholar
  37. [37]
    R. McCready: Real-Time Face Detection on a Configurable Hardware Platform; Master thesis, University of Toronto, 2000Google Scholar
  38. [38]
    T. Fry, S. Hauck: Hyperspectral Image Compression on Reconfigurable Platforms; Proceedings of FCCM 2002Google Scholar
  39. [39]
    P. Buxa, D. Caliga: Reconfigurable Processing Design Suits UAV Radar Apps; COTS J., October 2005: [40]Google Scholar
  40. [40]
  41. [41]
  42. [42]
    R. Porter: Evolution on FPGAs for Feature Extraction; Ph.D.thesis; Queensland University, Brisbane, Australia, 2001: [43]Google Scholar
  43. [43]
  44. [44]
    E. Chitalwala: Starbridge Solutions to Supercomputing Problems; RSSI Reconfigurable Systems Summer Institute, July 11-13, 2005, UrbanaChampaign, IL,USAGoogle Scholar
  45. [45]
    S.D. Haynes, P.Y.K. Cheung, W. Luk, J. Stone: SONIC - A Plug-In Architecture for Video Processing; Proceedings of FPL 1999Google Scholar
  46. [46]
    M. Kuulusa: DSP Processor Based Wireless System Design; Tampere University of Technology, Publ. #296: [47]Google Scholar
  47. [47]
  48. [48]
    B. Sch äfer, S. Quigley, A. Chan: Implementation of The DiscreteElement Method Using Reconfigurable Computing (FPGAs); 15th ASCE Engineering Mechanics Conference, June 2-5, 2002, New York, NY: [49]Google Scholar
  49. [49]
  50. [50]
    G.Lienhart:BeschleunigungHydrodynamischer N-K örper-Simulationenmit Rekonfigurierbaren Rechenystemen;33rd Speedup/19th PARSWorksh.; Basel, Switzerland, March 19-21, 2003Google Scholar
  51. [51]
    G. Steiner, K. Shenoy, D. Isaacs, D. Pellerin: How to accelerate algo-rithms by automatically generating FPGA coprocessors; Dr. Dobbs Portal, August 09, 2006 URL: [52]Google Scholar
  52. [52]
  53. [53]
    R. Hartenstein (keynote): The Transdisciplinary Responsibility of CS Curricula; 8th World Conference on Integrated Design & Process Tech-nology (IDPT), June 25-29, 2006, San Diego, CA, USAGoogle Scholar
  54. [54]
    R. Hartenstein (invited presentation): Reconfigurable Computing; Com-puting Meeting, Commission of the EU, Brussels, Belgium, May 18, 2006,Google Scholar
  55. [55]
    R. Hartenstein (keynote): New horizons of very high performance com-puting (VHPC) - hurdles and chances; 13th Reconfigurable Architec-tures Workshop (RAW 2006), Rhodos Island, Greece, April 25-26, 2006Google Scholar
  56. [56]
    R. Hartenstein: Configware f ür Supercomputing: Aufbruch zum Per-sonal Supercomputer; PIK - Praxis der Informationsverarbeitung und Kommunikation, 2006; KG Saur Verlag GmbH, Munich, Germany -title in English: see [57]Google Scholar
  57. [57]
    Configware for Supercomputing: Decampment for the Personal Super-computerGoogle Scholar
  58. [58]
    J. Becker et al.: An Embedded Accelerator for Real Time Image Processing;8th EUROMI-CRO Workshop on Real Time Systems, L’Aquila, Italy, June 1996Google Scholar
  59. [59]
  60. [60]
    W. Nebel et al.: PISA, a CAD Package and Special Hardware for Pixel-oriented Layout Analysis; ICCAD 1984Google Scholar
  61. [61]
    J. Becker et al.: High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, Wiley, 1996Google Scholar
  62. [62]
  63. [63]
  64. [64]
    R. Hartenstein (opening keynote): The Re-definition of Low Power Design for HPC: A Paradigm Shift; 19th Symposium on Integrated Circuits and System Design (SBCCI 2006), August 28-September 1, 2006, Ouro Preto, Minas Gerais, BrazilGoogle Scholar
  65. [65]
    Ch. Piguet (keynote): Static and dynamic power reduction by architec-ture selection; PATMOS 2006, September 13-15, Montpellier, FranceGoogle Scholar
  66. [66]
    V. George, J. Rabaey: Low-Energy FPGAs: Architecture and Design; Kluwer, 2001Google Scholar
  67. [67]
    R. Hartenstein (opening keynote address: The Re-definition of Low Power Digital System Design - for slashing the Electricity Bill by Millions of Dollars; The 19th Symposium on Integrated Circuits and System Design (SBCCI 2006), August 28-September 1, 2006, Ouro Preto, Minas Gerais, BrazilGoogle Scholar
  68. [68]
    R. Hartenstein(invited contribution): Higher Performance by lessCPUs; HPCwire, June 30, 2006, in conjunction with ISC 2006, Dresden, Germany - [69]Google Scholar
  69. [69]
  70. [70]
    R. Hartenstein, A. Nu ñez et al.: Report on Interconnect Modelling: Second Periodic Progress Report; PATMOS Project, Universit ät Kaiserslautern, December 1991Google Scholar
  71. [71]
  72. [72]
  73. [73]
    N.N.: R. Associates Joins Nallatech’s Growing Channel Partner Pro-gram; Companies are Using FPGAs to Reduce Costs and Increase Per-formance in Seismic Processing for Oil and Gas Exploration; FPGA and Structured ASIC Journal BusinessWire, August 08, 2005 - URL: [74]Google Scholar
  74. [74]
  75. [75]
    R. Hartenstein (invited presentation): Reconfigurable Computing (RC) being Mainstream: Torpedoed by Education; 2005 International Conference on Microelectronic Systems Education, June 12-13, 2005, Anaheim, California, co-located with DAC (Design Automation Conference) 2005Google Scholar
  76. [76]
    R. Hartenstein (invited opening keynote address): Reconfigurable HPC: Torpedoed by Deficits in Education? Workshop on Reconfigurable Sys-tems for HPC (RHPC); July 21, 2004, to be held in conjunction with HPC Asia 2004, 7th International Conference on High Performance Computing and Grid in Asia Pacific Region, July 20-22, 2004, Omiya (Tokyo), JapanGoogle Scholar
  77. [77]
    R. Hartenstein (keynote): The Changing Role of Computer Architecture Education within CS Curricula; Workshop on Computer Architecture Education (WCAE 2004) June 19, 2004, in conjunction with the 31st International Symposiam on Computer Architecture (ISCA), Munich, Germany, June 19-23, 2004Google Scholar
  78. [78]
    S. Hauck: The Role of FPGAs in Reprogrammable Systems; Proceed-ings of IEEE, 1998Google Scholar
  79. [79]
    F. Rammig (interview): Visions from the IT Engine Room; IFIP TC 10-Computer Systems Technology, URL: [80]Google Scholar
  80. [80]
  81. [81]
    S. Hang: Embedded Systems- Der(verdeckte) Siegeszug einerSchl üsseltechnologie; Deutsche Bank Research, January 2001, [82],URL: [83]Google Scholar
  82. [82]
    S. Hang ([81] title in English): Embedded Systems - The (subsurface)Triumph of a Key Technology;Google Scholar
  83. [83]
  84. [84]
    P. Gillick: State of the art FPGA development tools; ReconfigurableComputing Workshop, Orsay, France, September 2003Google Scholar
  85. [85]
  86. [86]
    V. Betz, J. Rose, A. Marquardt (editors): Architecture and CAD forDeep-Submicron FPGas; Kluwer, 1999Google Scholar
  87. [87]
    R. Hartenstein: Morphware and Configware;(invited chapter) in:A. Zomaya (editor): Handbook of Innovative Computing Paradigms;Springer Verlag, New York, 2006Google Scholar
  88. [88]
    S. Hoffmann: Modern FPGAs, Reconfigurable Platforms and Their Design Tools; Proceedings REASON Summer School; Ljubljana, Slovenia, August 11-13, 2003Google Scholar
  89. [89]
    N.N.: Pair extend Flash FPGA codevelopment pact; http://www.electronicstalk.com/news/act/act120.html
  90. [90]
    B. Lewis, Gartner Dataquest, October 28, 2002Google Scholar
  91. [91]
  92. [92]
  93. [93]
  94. [94]
    D. Soudris et al.: Survey of existing fine grain reconfigurable hardware platforms; Deliverable D9, AMDREL consortium (Architectures and Methodologies for Dynamically Reconfigurable Logic); 2002Google Scholar
  95. [95]
    J. Oldfield, R. Dorf: Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems; Wiley-Interscience, 1995Google Scholar
  96. [96]
    J. Rose, A.E. Gamal, A. Sangiovanni-Vincentelli: Architecture of FP-GAs; Proceedings of IEEE, 81(7), July 1993Google Scholar
  97. [97]
  98. [98]
  99. [99]
    N.N.: FPGA Development Boards and Software for Universities; Micro-electronic System News, August 2, 2006, URL: [100]Google Scholar
  100. [100]
  101. [101]
    S. Davidmann: Commentary: It’s the software, stupid; El. Bus. online;August 15, 2006, URL: [102]Google Scholar
  102. [102]
  103. [103]
    Michio Kaku: Visions; Anchor Books, 1998Google Scholar
  104. [104]
    U. R üde: Technological trends and their impact on the future of supercomputers; in: H. Bungartz, F Durst, C. Zenger, C. (editors): High Performance Scientific and Engineering Computing: International FORTWIHR Conference on HPSEC, Munich, Germany, March 16-18, 1998- URL: [112]Google Scholar
  105. [105]
    F. Brooks: No Silver Bullet; COMPUTER, 20, 4 (April 1987)Google Scholar
  106. [106]
    F. Brooks: The Mythical Man Month (Anniversary Edition with 4 newchapters) Addison Wesley, 1995Google Scholar
  107. [107]
    T.S. Kuhn: The Structure of Scientific Revolution; University of ChicagoPress, Chicgo, 1996Google Scholar
  108. [108]
    V. Rajlich: Changing the Paradigm of Software Engineering; C. ACM49,8(August 2006)Google Scholar
  109. [109]
    E.M. Rogers: Diffusion of Innovations - 4th edition; The Free Press,New York, 1995Google Scholar
  110. [110]
  111. [111]
  112. [112]
  113. [113]
    V. Natoli: A Computational Physicist’s View of Reconfigurable HighPerformance Computing; Reconfigurable Systems Summer Institute,Google Scholar
  114. Urbana, IL, July 2005, URL: [115]Google Scholar
  115. [114]
    Edward A. Lee: The Problem with Threads; COMPUTER, May 2006Google Scholar
  116. [115]
  117. [116]
    Mark Bereit: Escape the Software Development Paradigm Trap; Dr.Dobb’s Journal (05/29/06)Google Scholar
  118. [117]
    B. Hayes: The Semicolon Wars; American Scientist, July/August 2006URL: [118]Google Scholar
  119. [118]
  120. [119]
    E. Levenez: Computer Languages History; http://www.levenez.com/lang/
  121. [120]
    B. Kinnersley: The Language List - Collected Information on About2500 Computer Languages, Past and Present; http://people.ku.edu/∼nkinners/LangList/Extras/langlist.htm
  122. [121]
    D. Piggott: HOPL: An interactive roster of programming languages;1995-2006. URL: [122]Google Scholar
  123. [122]
  124. [123]
    G. Koch, R. Hartenstein: The Universal Bus considered harmful; in:[124]Google Scholar
  125. [124]
    R. Hartenstein R. Zaks (editors): Microarchitecture of Computer Sys-tems; American Elsevier, New York, 1975Google Scholar
  126. [125]
    R. Hartenstein (opening keynote address): Why We Need Reconfig-urable Computing Education: Introduction; The 1st International Workshop on Reconfigurable Computing Education (RCeducation 2006), March 1, 2006, Karlsruhe, Germany - in conjunction with the IEEE Computer Society Annual Symposiun on VLSI (ISVLSI 2006), March 2-3, 2006, Karlsruhe, Germany [126]Google Scholar
  127. [126]
  128. [127]
    A. Reinefeld(interview): FPGAs in HPC Mark “Beginning of aNew Era”; HPCwire June 29, 2006 - http://www.hpcwire.com/hpc/
  129. 709193.htmlGoogle Scholar
  130. [128]
    N. Petkov: Systolic Parallel Processing; North-Holland, 1992Google Scholar
  131. [129]
    H.T. Kung: Why Systolic Architectures? IEEE Computer, 15(1) 37-46(1982)Google Scholar
  132. [130]
    R. Kress et al.: A Datapath Synthesis System (DPSS) for the Reconfig-urable Datapath Architecture; Proceedings of ASP-DAC 1995Google Scholar
  133. [131]
  134. [132]
    M. Herz et al. (invited p.): Memory Organization for Data-Stream-based Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS), September 15-18, 2002, Dubrovnik, CroatiaGoogle Scholar
  135. [133]
  136. [134]
    M. Herz et al.: A Novel Sequencer Hardware for Application SpecificComputing; ASAP’97Google Scholar
  137. [135]
    M. Herz: High Performance Memory Communication Architectures for Coarse-grained Reconfigurable Computing Systems; Dissertation, University of Kaiserslautern, 2001, URL: [136]Google Scholar
  138. [136]
  139. [137]
    U. Nageldinger et al.: Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures: International Conference on Field Programmable Logic and Applications (FPL) August 28-30 2000, Villach, AustriaGoogle Scholar
  140. [138]
    U. Nageldinger Coarse-grained Reconfigurable Architectures Design Space Exploration; Dissertation, University of Kaiserslautern, 2001, Kaiserslautern, Germany URL: [139]Google Scholar
  141. [139]
  142. [140]
    R. Hartenstein (invited plenum presentation): Reconfigurable Super-computing: Hurdles and Chances; International Supercomputer Con-ference (ICS 2006), June 28-30, 2006, Dresden, Germany - http://www.supercomp.de/
  143. [141]
  144. [142]
    A. Ast et al.: Data-procedural languages for FPL-based Machines;International Conference on Field Programmable Logic and Applica-tions (FPL), September 7-9, 1994, Prag, TschechiaGoogle Scholar
  145. [143]
    J. Becker et al.: Parallelization in Co-Compilation for ConfigurableAccelerators; Asian-Pacific Design Automation Conference(ASP-DAC), February 10-13, 1998, Yokohama, JapanGoogle Scholar
  146. [144]
    J. Becker: A Partitioning Compiler for Computers with Xputer-basedAccelerators, Dissertation, University of Kaiserslautern, 1997, URL:[145]Google Scholar
  147. [145]
  148. [146]
    K. Schmidt: A Program Partitioning, Restructuring, and Mapping Method for Xputers, Dissertation, University of Kaiserslautern, 1994 URL: [147]Google Scholar
  149. [147]
  150. [148]
    J.C. Hoe, Arvind: Hardware Synthesis from Term Rewriting Systems;VLSI’99, Lisbon, PortugalGoogle Scholar
  151. [149]
    M. Ayala-Rinc ón, R. Hartenstein, C.H. Llanos, R.P. Jacobi: Prototyping Time and Space Efficient Computations of Algebraic Operations over Dynamically Reconfigurable Systems Modeled by Rewriting-Logic; accepted for ACM Transactions on Design Automation of Electronic Systems (TODAES), 2006Google Scholar
  152. [150]
    A. Cantle: Is it time for von Neumann and Harvard to retire? RSSI Reconfigurable Systems Summer Institute, July 11-13, 2005, UrbanaChampaign, IL, USAGoogle Scholar
  153. [151]
  154. [152]
  155. [153]
    S. Heath: Embedded Systems Design, Elsevier, 2003Google Scholar
  156. [154]
    F. Catthoor et al.: Data Access and Storage Management for EmbeddedProgrammable Processors; Kluwer, 2002Google Scholar
  157. [155]
    A.G. Hirschbiel et al.: A Novel Paradigm of Parallel Computation and Its Use to Implement Simple High Performance Hardware; InfoJapan’90 - International Conference memorating 30th Anniversary, Computer Society of Japan; Tokyo, Japan, 1990Google Scholar
  158. [156]
    Invited reprint of [155] in Future Generation Computer Systems 791/92, pp. 181-198, North HollandGoogle Scholar
  159. [157]
    W. Nebel et al.: Functional Design Verification by Register Transfer NetExtraction from Integrated Circuit Layout Data; IEEE COMPEURO,Hamburg, 1987Google Scholar
  160. [158]
    C. Chang et al.: The Biggascale Emulation Engine (Bee); summerretreat 2001, UC BerkeleyGoogle Scholar
  161. [159]
    H. Simmler et al.: Multitasking on FPGA Coprocessors; International Conference on Field Programmable Logic and Applications (FPL), August 28-30, 2000, Villach, AustriaGoogle Scholar
  162. [160]
    H. Walder, M. Platzner: Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations; Proceedings of ERSA 2003Google Scholar
  163. [161]
    P. Zipf: A Fault Tolerance Technique for Field-Programmable Logic Arrays; Dissertation, University of Siegen, 2002Google Scholar
  164. [162]
    M. Abramovici, C, Stroud: Improved BIST-Based Diagnosis of FPGA Logic Blocks; IEEE International Test Conference, Atlantic City, October 2000Google Scholar
  165. [163]
    J.A. Starzyk, J. Guo, Z. Zhu: Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-organizing Learning Array; International Journal on Embedded Systems, 2006Google Scholar
  166. [164]
    M. Glesner, W. Pochmueller: An Overview of Neural Networks inVLSI; Chapman & Hall, London, 1994Google Scholar
  167. [165]
    N. Ambrosiano: Los Alamos and Surrey Satellite contract for Cibolaflight experiment platform; Los Alamos National Lab, Los Alamos,NM, March 10, 2004, URL: [166]Google Scholar
  168. [166]
  169. [167]
    M. Gokhale et al.: Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs; IPDPS 2004Google Scholar
  170. [168]
    G. De Micheli (keynote): Nanoelectronics: challenges and opportuni-ties; PATMOS 2006, September 13-15, Montpellier, FranceGoogle Scholar
  171. [169]
    E. Venere: Nanoelectronics Goes Vertical; HPCwire, August 4, 2006,15(3)- http://www.hpcwire.com/hpc/768349.html
  172. [170]
    J.E. Savage: Research in Computational Nanotechnology; Link: [171]Google Scholar
  173. [171]
  174. [172]
    A. DeHon et al.: Sub-lithographic Semiconductor Computing Systems;HotChips-15, August 17-19, 2003, link: [173]Google Scholar
  175. [173]
  176. [174]
    L. Gottlieb, J.E. Savage, A. Yerukhimovich: Efficient Data Storage inLarge Nanoarrays; Theory of Computing Systems, 38, pp. 503-536,Google Scholar
  177. [175]
    J.E. Savage: Computing with Electronic Nanotechnologies; 5th Confer-ence on Algorithms and Complexity, May 28-30, 2003, Rome, ItalyGoogle Scholar
  178. [176]
    International Technology Roadmap for Semiconductors. link: [177]Google Scholar
  179. [177]
  180. [178]
    A. DeHon, P. Lincoln, J. Savage: Stochastic Assembly of Sublitho-graphic Nanoscale Interfaces; IEEE Transactions in Nanotechnology, September 2003.Google Scholar
  181. [179]
    Y. Cui et al.: Diameter-Controlled Synthesis of Single Crystal SiliconGoogle Scholar
  182. Nanowires; Applied Physics Letters, 78(15):2214-2216, 2001.Google Scholar
  183. [180]
    A.M. Morales, C.M. Lieber: A Laser Ablation Method for Synthesis of Crystalline Semi-conductor Nanowires; Science, 279:208-211, 1998.Google Scholar
  184. [181]
    M.S. Gudiksend et al.: Epitaxial Core-Shell and Core-Multi-Shell Nanowire Heterostructures; Nature, 420:57-61, 2002.Google Scholar
  185. [182]
    M.S. Gudiksen et al.: Growth of Nanowire Superlattice Structures for Nanoscale Photonics and Electronics;. Nature, 415:617-620, February 7,2002.Google Scholar
  186. [183]
    C. Collier et al.: A Catenane-Based Solid State Reconfigurable Switch;Science, 289:1172-1175, 2000.Google Scholar
  187. [184]
    C.P. Collier et al.: Electronically Configurable Molecular-Based LogicGates. Science, 285:391-394, 1999.Google Scholar
  188. [185]
    A. DeHon: Array-Based Architecture for FET-based Nanoscale Elec-tronics; IEEE Transactions on Nanotechnology, 2(1):23-32, MarchGoogle Scholar
  189. [186]
    C.L. Brown et al.: Introduction of [2] Catenanes into Langmuir Films and Langmuir-Blodgett Multilayers. A Possible Strategy for Molecular Information Storage Materials; Langmuir, 16(4):1924-1930, 2000.Google Scholar
  190. [187]
    Y. Huang, X. Duan, Q. Wei, C.M. Lieber: Directed Assembley of One-Dimensional Nanostructures into Functional Networks. Science, 291:630-633, January 26, 2001.Google Scholar
  191. [188]
    D. Whang, S. Jin, C.M. Lieber: Nanolithography Using Hierarchically Assembled Nanowire Masks; Nano Letters, 3, 2003. links: [205]Google Scholar
  192. [189]
    R. Hartenstein (invited embedded tutorial): A Decade of Reconfigurable Computing: A Visionary Retrospective; Design, Automation and Test in Europe, Conference & Exhibition (DATE 2001), March 13-16, 2001, Munich, GermanyGoogle Scholar
  193. [190]
  194. [191]
    R. Hartenstein et al.1 : A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24 Hawaii International Conference on System Sciences, Koloa, Hawaii, January 1991Google Scholar
  195. [192]
    J. Hoogerbrugge, H. Corporaal, H. Mulder: Software pipelining for transport-triggered architectures: Proceedings of MICRO-24, Albuquerque, 1991Google Scholar
  196. [193]
    H. Corporaal: Microprocessor Architectures from VLIW to TTA; JohnWiley, 1998Google Scholar
  197. [194]
  198. [195]
    D. Tabak, G.J. Lipovski: MOVE architecture in digital controllers; IEEE Transactions on Computers C-29, pp. 180-190, 1980Google Scholar
  199. [196]
    D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, K. Yelick: A Case for Intelligent RAM; IEEE Micro, March/April 1997.Google Scholar
  200. [197]
    J. Dongarra et al. (editors): The Sourcebook of Parallel Computing;Morgan Kaufmann 2002Google Scholar
  201. [198]
    G. Amdahl: Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities; Proceedings of AFIPS 1967Google Scholar
  202. [199]
    C.A.R. Hoare: Communicating Sequential Processes, Prentice-Hall, 1985- URL: [200]Google Scholar
  203. [200]
  204. [201]
  205. [202]
    Th. Steinke: Experiences with High-Level-Programming of FPGAs;International Supercomputer Conference(ICS2006), June28-30,2006, Dresden, GermanyGoogle Scholar
  206. [203]
    N. Wehn (invited keynote): Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems; IEEE Computer Society Annual Symposium on VLSI, March 2-3, 2006, Karlsruhe, GermanyGoogle Scholar
  207. [204]
  208. [205]
  209. [206]
    Joint Task Force for Computing Curricula 2004: Computing Curricula2004. Overview Report; s. [207]Google Scholar
  210. [207]
  211. [208]
  212. [209]
  213. [210]
    Tracy Kidder: The Soul of A New Machine; Little Brown and Company,1981- reprint: [211]Google Scholar
  214. [211]
    Tracy Kidder (reprint): The Soul of A New Machine; Modern Library,1997Google Scholar
  215. [212]

Copyright information

© Springer 2007

Authors and Affiliations

  • Reiner Hartenstein
    • 1
  • Tu Kaiserslautern
    • 1
  1. 1.Kaiserslautern University of TechnologyGermany

Personalised recommendations