Synthesis of Designs – Synplify Tool

In the previous chapter, we learnt the design flow of VLSI circuits. This was followed by a discussion on design methodology for solving problems effectively. We gained hands on experience on the simulation tool and verified our designs presented earlier. Designs are meaningful only if they are mapped on to a target chip such as an FPGA. The present chapter deals with a synthesis tool, which not only maps the HDL design on an FPGA but also brings about an efficient optimization of logic, thus conserving a substantial number of gates.