RTL Coding Guidelines

We have so far seen how to model combinational and sequential circuits in Verilog, which are vital ingredients in any digital VLSI system design. The ultimate aim of the designer is to finally map the design on an FPGA device or implement as an ASIC, and this is possible only if you follow certain guidelines. A popular guideline is known as the RTL Coding Guideline, where RTL stands for Register Transfer Level, signifying that data transfers in a system take place via registers [17]. It is basically adhering to synchronous design practices, and it signifies the regulation of data flow, and how the data is processed. Since we deal with a syndigital chronous design, it should run smoothly through Simulation, Synthesis, and finally on place and route tools, which we will learn in subsequent chapters. In order to do this, we have to isolate the asynchronous and sequential circuits. The combinational circuits fall under the category of asynchronous circuits. We have actually followed the RTL coding style in our designs dealt in an earlier chapter. Therefore, the codes developed there will run smoothly in all the tools mentioned above.