Implementation of floating point arithmetics using an FPGA

Abstract

Floating point operations, which find their applications in vast areas such as many mathematical optimization methods, digital signal and image processing algorithms, and Artificial Neural Networks (ANNs), require much area and time for ordinary implementation on Field Programmable Gate Arrays (FPGAs). However, meaningful floating point arithmetic implementation on FPGAs is quite difficult with low level design specifications due to mapping difficulties and the complexity of floating point arithmetic. Design and implementation of floating point arithmetic and mapping of this into an FPGA become easier with the emergence of new generation FPGAs and development of high level languages such as VHDL tools. This paper presents the implementation methodologies of various floating point arithmetic operations such as addition, subtraction, multiplication, and division using 32-bit IEEE 754 floating point format. The implementation is performed using Xilinxs Spartan 3 FPGAs. The algorithms and implementation steps used for different operations are discussed in detail. As an example, an ANN application is presented using these algorithms.