Abstract
This chapter is dedicated to the effects of radiation on programmable circuits. It is described the radiation effects on integrated circuits manufactured using CMOS process and it is explained in detail the difference between the effects of a SEU in an ASIC and in a SRAM-based FPGA architecture. It is also discussed some SEU mitigation techniques that can be applied at the FPGA architectural level. The problem of protecting SRAM-based FPGAs against radiation in the high level description is also defined.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Nasa. Radiation Effects on Digital Systems. USA, 2002. Available at: < radhome. gsfc.nasa.gov/top.htm >. Visited on January, 2006.
Sia Semiconductor Industry Association. The National Technology Roadmap for Semiconductors. USA, 1994.
Johnston, A. Scaling and Technology Issues for Soft Error Rates. In Research Conference On Reliability, 4., 2000. Proceedings. Palo Alto: Stanford University, 2000.
O’Bryan, M. et al. Current single event effects and radiation damage results for candidate spacecraft electronics. In IEEE Radiation Effects Data Workshop, 2002. Proceedings. [S.l.]: IEEE Computer Society, 2002. p. 82–105.
Barth, J. Applying Computer Simulation Tools to Radiation Effects Problems. In IEEE Nuclear Space Radiation Effects Conference, NSREC, 1997. Proceedings. [S.l.]: IEEE Computer Society, 1997. p. 1–83.
Normand, E. Single event upset at ground level. IEEE Transactions on Nuclear Science, New York, v.43, n.6, p. 2742–2750, Dec. 1996.
Dupont, E.; Nicolaidis, M.; Rohr, P. Embedded robustness IPs for transient-error-free ICs. IEEE Design & Test of Computers, New York, v.19, n.3, p. 54–68, May-June 2002.
Alexandrescu, D.; Anghel, L.; Nicolaidis, M. New methods for evaluating the impact of single event transients in VDSM ICs. In: IEEE International Symposium On Defect And Fault Tolerance in VLSI Systems Workshop, DFT, 17., 2002. Proceedings. [S.l.]: IEEE Computer Society, 2002. p. 99–107.
Leavy, J. et al. Upset due to a single particle caused propagated transient in a bulk CMOS microprocessor. IEEE Transactions on Nuclear Science, New York, v.38, n.6, p. 1493–1499, Dec. 1991.
Hass, J. Probabilistic Estimates of Upset Caused by Single Event Transients. In Nasa Symposium on VLSI Design, 8., 1999. Proceedings. [S.l.: s.n.], 1999.
Guntzel, J., Functional Timing Analysis of VLSI Circuits Containing Complex Gates, Doctoral Thesis, Instituto de Informatica, UFRGS, Porto Alegre, Brazil, 2001.
Xilinx, Inc. Virtex(r)(tm) 2.5 V Field Programmable Gate Arrays: Datasheet DS003. USA, 2000.
Rebaudengo, M.; Reorda, M.S.; Violante, M. Simulation-based Analysis of SEU effects of SRAM-based FPGAs. In International Workshop On Field-Programmable Logic And Applications, FPL, 2002. Proceedings. [S.l.]: IEEE Computer Society, 2002. p. 607–615.
Caffrey, M.; Graham, P.; Johnson, E. Single Event Upset in SRAM FPGAs. In Military and Aerospace Applications of Programmable Logic Conference, MAPLD, 2002. Proceedings. [S.l.: s.n.], 2002.
Fuller, E. et al. Radiation test results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing. In International Conference on Military and Aerospace Applications of Programmable Logic Devices, MAPLD, 2002. Proceedings. [S.l.: s.n.], 2002.
Carmichael, C.; Fuller, E.; Fabula, J.; Lima, F. Proton Testing of SEU Mitigation Methods for the Virtex(r) FPGA. In International Conference on Military and Aerospace Applications of Programmable Logic Devices, MAPLD, 2001. Proceedings. [S.l.: s.n.], 2001.
Ohlsson, M.; Dyreklev, P.; Johansson, K.; Alfke, P. Neutron Single Event Upsets in SRAM based FPGAs. In IEEE Nuclear Space Radiation Effects Conference, NSREC, 1998. Proceedings. [S.l.]: IEEE Computer Society, 1998.
Canaris, J.; Whitaker, S. Circuit techniques for the radiation environment of space. In Custom Integrated Circuits Conference, 1995. Proceedings. [S.l.]: IEEE Computer Society, 1995, p. 77–80.
Anghel, L.; Alexandrescu, D.; Nicolaidis, M. Evaluation of a soft error tolerance technique based on time and/or space redundancy. In Symposium on Integrated Circuits and Systems Design, SBCCI, 13., 2000. Proceedings. Los Alamitos : IEEE Computer Society, 2000. p. 237–242.
Mavis, D.; Eaton, P. SEU and SET Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design. In International Conference on Military and Aerospace Applications of Programmable Logic Devices, MAPLD, 2000. Proceedings. [S.l.: s.n.], 2000.
Rockett, L. R. An SEU-hardened CMOS data latch design. IEEE Transactions on Nuclear Science, New York, v.35, n.6, p. 1682–1687, Dec. 1988.
Whitaker, S.; Canaris, J.; Liu, K. SEU hardened memory cells for a CCSDS Reed-Solomon encoder. IEEE Transactions on Nuclear Science, New York, v.38, n.6, p. 1471–1477, Dec. 1991.
Calin, T.; Nicolaidis, M.; Velazco, R. Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science, New York, v.43, n.6, p. 2874–2878, Dec. 1996.
Weaver, H.; et al. An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM. IEEE Transactions on Nuclear Science, New York, v.34, n.6, Dec. 1987.
Rockett, L. R. A design based on proven concepts of an SEU-immune CMOS configurable data cell for reprogrammable FPGAs. Microelectronics Journal, Elsevier, v.32, p. 99–111, 2001.
Houghton, A. D. The Engineer’s Error Coding Handbook. London: Chapman & Hall, 1997.
Redinbo, G.; Napolitano, L.; Andaleon, D. Multi-bit Correcting Data Interface for Fault-Tolerant Systems. IEEE Transactions on Computers, New York, v.42, n.4, p. 433–446, Apr. 1993.
Neuberger, G.; Lima, F.; Carro, L.; Reis, R. A Multiple Bit Upset Tolerant SRAM Memory. Transactions on Design Automation of Electronic Systems, TODAES, New York, v.8, n.4, Oct. 2003.
Xilinx, Inc. QPRO(tm)Virtex(r)(tm) 2.5V Radiation Hardened FPGAs: Application Notes 151. USA, 2000.
Xilinx Inc. Virtex(r) Series Configuration Architecture User Guide: Application Notes 151. USA, 2000.
Carmichael, C. Triple Module Redundancy Design Techniques for Virtex(r) Series FPGA: Application Notes 197. San Jose, USA: Xilinx, 2000.
Lima, F.; Carmichael, C.; Fabula, J.; Padovani, R.; Reis, R. A fault injection analysis of Virtex FPGA TMR design methodology. In European Conference on Radiation and Its Effects on Components and Systems, RADECS, 2001. Proceedings. [S.l.]: IEEE Computer Society, 2001b. p. 275–282.
M. Sonza Reorda, L. Sterpone, M. Violante, “Multiple errors provoked by SEUs in the FPGA configuration memory: a possible solution”, 10th IEEE European Test Symposium, 2005.
Kastensmidt, F. L.; Kinzel Filho, C.; Carro, Luigi. Improving Reliability of SRAM Based FPGAs by Inserting Redundant Routing. IEEE Transactions on Nuclear Science, New York, v. 53, n. 4, 2006.
Kastensmidt, F. L., Carro, Luigi, Sterpone, L., Reorda, M. On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs In: Proceedings in Design Automation and Test in Europe (DATE). New York: IEEE, 2005.
D’Angelo, S.; Metra, C.; Pastore, S.; Pogutz, A.; Sechi, G.R. Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1998. p. 233–240.
Lubaszewski, M.; Courtois, B.; A reliable fail-safe system, IEEE Transactions on Computers, Volume: 47 Issue: 2, Feb. 1998, P. 236–241.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer
About this chapter
Cite this chapter
Kastensmidt, F.L., Reis, R. (2007). Fault Tolerance in Programmable Circuits. In: VELAZCO, R., FOUILLAT, P., REIS, R. (eds) Radiation Effects on Embedded Systems. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5646-8_8
Download citation
DOI: https://doi.org/10.1007/978-1-4020-5646-8_8
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-5645-1
Online ISBN: 978-1-4020-5646-8
eBook Packages: EngineeringEngineering (R0)