Error Rate Prediction of Digital Architectures: Test Methodology and Tools
Evaluating the sensitivity to Single Event Effects of programmable digital integrated circuits (i.e. microprocessors, digital signal processors and field programmable gate arrays) requires specific methodologies and dedicated tools. Indeed, such an evaluation is based on data gathered from tests performed on-line during which the target circuit is exposed to a flux of particles having features (energy, range in Silicon) somewhat representative of the ones the circuit will encounter in its final environment. These experiments, usually called accelerated radiation ground testing, are performed by means of appropriate radiation facilities entailing thus significant development efforts and cost impact. In this chapter an approach will be presented, describing the corresponding hardware as well as software tools developed to deal with such experiments at a reasonable cost versus effort trade-off.
KeywordsFault Injection Memory Element Sensitive Volume Program Counter Device Under Test
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