Layout-Aware Circuit Sizing
This chapter completes the description and demonstration of the reuse-based design framework presented here. It basically delves into the why and how of including layout geometric information and layout-induced parasitics within the optimization loop of the cell-level sizing process. Outlined in Chapter 2, these sizing techniques, namely geometrically constrained sizing and parasitic- aware sizing, are now the object of the present chapter.
KeywordsShape Function Area Loss Layout Generation Circuit Size Capacitive Parasitics
Unable to display preview. Download preview PDF.