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Layout-Aware Circuit Sizing

  • R. CASTRO-LÓPEZ
  • F.V. FERNÁNDEZ
  • O. GUERRA-VINUESA
  • Á. RODRÍGUEZ-VÁZQUEZ

Abstract

This chapter completes the description and demonstration of the reuse-based design framework presented here. It basically delves into the why and how of including layout geometric information and layout-induced parasitics within the optimization loop of the cell-level sizing process. Outlined in Chapter 2, these sizing techniques, namely geometrically constrained sizing and parasitic- aware sizing, are now the object of the present chapter.

Keywords

Shape Function Area Loss Layout Generation Circuit Size Capacitive Parasitics 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2006

Authors and Affiliations

  • R. CASTRO-LÓPEZ
    • 1
  • F.V. FERNÁNDEZ
    • 2
  • O. GUERRA-VINUESA
    • 3
  • Á. RODRÍGUEZ-VÁZQUEZ
    • 4
  1. 1.IMSE-CNM-CSICSpain
  2. 2.IMSE-CNM-CSICUniversity of SevilleSpain
  3. 3.University of SevilleSpain
  4. 4.University of SevilleSpain

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