Abstract
Electrostatic discharge, or ESD, has been referred to as a “pervasive reliability concern” for ICs [1] because there are so many different scenarios under which an integrated circuit may lie in the path of a static discharge. For example, a person may acquire static charge by walking across a carpet and then dissipate this charge by picking up an IC and plugging it into a grounded socket. The IC may itself acquire static charge, for example, by sliding down a plastic shipping tube, and this charge will dissipate when the IC first contacts a conductor. These events would be described by the Human Body Model and the Charged Device Model, respectively [2]. Human Body Model type events are characterized by a risetime of about 10 ns, duration of about 150 ns, and peak current on the order of a few amperes. Charged Device Model type events are characterized by a risetime of about 250 ps, duration of 1-2 ns, and a peak current of about 10 A. RF transistors are designed to operate at milliamp current levels, and if the ESD current were to pass through one of these devices, it would be destroyed, leading to circuit failure. Therefore, between any arbitrary pair of pins, a safe path must be provided for dissipation of static charge. This is achieved by on-chip ESD protection circuits.
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References
C. Duvvury and A. Amerasekera, “ESD: a pervasive reliability concern for IC technologies,” Proc. IEEE, vol. 81, no. 5, pp. 690–702, 1993.
A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, 2nd ed., John Wiley & Sons, 2002.
J. Miller, “SPICE-based ESD protection design utilizing diodes and active MOSFET rail clamp circuits,” 2005 EOS/ESD Symposium Tutorial, 2005.
R. Merrill and E. Issaq, “ESD Design methodology,” Proc. EOS/ESD Symp., pp. 233–237, 1993.
J. Smith and G. Boselli, “A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS processes,” Proc. EOS/ESD Symp., pp. 8–16, 2003.
M. Stockinger, et al., “Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies,” Proc. EOS/ESD Symp., pp. 17–26, 2003.
J. Li, R. Gauthier, and E. Rosenbaum, “A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection.” Proc. EOS/ESD Symp., pp. 273–279, 2004.
C. Torres, J. Miller, M. Stockinger, M. Akers, M. Khazhinksy, and J. Weldon, “Modular, portable and easily simulated ESD protection networks for advanced CMOS technologies,” Proc. EOS/ESD Symp., pp. 82–95, 2001.
K. Chatty, et al., “Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond,” Proc. Int. Rel. Phys. Symp., pp. 98–105, 2005.
C. Richier, et al., “Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 µm CMOS process,” Proc. EOS/ESD Symp., pp. 251–259, 2000.
S. Hyvonen, S. Joshi, and E. Rosenbaum, “Comprehensive ESD protection for RF inputs,” Proc. EOS/ESD Symp., pp. 188–194, 2003.
S. Thijs, et al., “ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS - implementation concepts, constraints and solutions,” Proc. EOS/ESD Symp., pp. 40–49, 2004.
V. Vassilev, et al., “Co-design methodology to provide high ESD protection levels in advanced RF circuits,” Proc. EOS/ESD Symp., pp. 195–203, 2003.
S. Hyvonen and E. Rosenbaum, “Diode-based tuned ESD protection for 5.25-GHz LNAs,” Proc. EOS/ESD Symp., pp. 9–17, 2005.
E. Worley and A. Bakulin, “Optimization of input protection diode for high speed applications,” Proc. EOS/ESD Symp., pp. 62–72, 2002.
K. Bhatia, S. Hyvonen, and E. Rosenbaum, “A compact, ESD-protected, SiGe BiCMOS LNA for ultra-wideband applications,” manuscript in preparation.
A. Ismail and A. Abidi, “A 3 to 10 GHz LNA using a wideband LC-ladder matching network,” Proc. IEEE Int. Solid-State Circuits Conf., pp. 384–385, 2004.
T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., Cambridge University Press, 2004.
S. Hyvonen, K. Bhatia, and E. Rosenbaum, “An ESD-protected 2.45/5.25-GHz dual-band CMOS LNA with series LC loads and a 0.5-V supply,” Proc. IEEE RFIC Symp., pp. 43–46, 2005.
S. Hyvonen, Electrostatic Discharge Protection and Measurement Techniques for Radio Frequency Integrated Circuits, Ph.D. Thesis, University of Illinois at Urbana-Champaign, 2004.
P. Leroux and M. Steyaert, “High-performance 5.2GHz LNA with on-chip inductor to provide ESD protection,” Elec. Lett., vol. 37, no. 7, pp. 467–469, 2001.
S. Hyvonen, S. Joshi, and E. Rosenbaum, “A cancellation technique to provide ESD protection for multi-GHz RF inputs,” Electronics Letters, vol. 39, no. 3, pp. 284–286, 2003.
S. Joshi, S. Hyvonen, and E. Rosenbaum, “High-Q ESD protection devices for use at RF and broadband I/O pins,” IEEE Trans. Elec. Dev., vol. 52, no. 7, pp. 1484–1488, 2005.
C. Duvvury and C. Diaz, “Dynamic gate coupling of NMOS for efficient output ESD protection,” Proc. IEEE Int. Rel. Phys. Symp., pp. 141–150, 1992.
S. Joshi, P. Juliano, E. Rosenbaum, G. Kaatz, and S. M. Kang, “ESD protection for BiCMOS circuits,” Proc. IEEE Bipolar/BiCMOS Circuits and Technol. Mtg., pp. 218–221, 2000.
J. Barth, K. Verhaege, L. Henry, and J. Richner, “TLP calibration, correlation, standards and new techniques,” IEEE Trans. Elec. Pkg. Mfg., vol. 24, pp. 99–108, 2001.
S. Galal and B. Razavi, “Broadband ESD protection circuits in CMOS technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2334–2340, 2003.
S. Voldman, et al., “Test methods, test techniques and failure criteria for evaluation of ESD degradation of analog and radio frequency (RF) technology,” Proc. EOS/ESD Symp., pp. 92–100, 2002.
V. Vassilev, G. Groeseneken, S. Jenei, R. Venegas, M. Steyaert, and H. Maes, “Modelling and extraction of RF performance parameters of CMOS electrostatic discharge protection devices,” Proc. EOS/ESD Symp., pp. 111–118, 2002.
T. Maloney and N. Khuruna, “Transmission line pulsing technique for circuit modeling of ESD phenomena,” Proc. EOS/ESD Symp., pp. 49–54, 1985.
S. Hyvonen, S. Joshi, and E. Rosenbaum, “Combined TLP/RF testing system for detection of ESD failures in RF circuits,” IEEE Transactions on Electronics Packaging Manufacturing, vol. 28, no. 3, pp. 224–230, 2005
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Rosenbaum, E., Hyvonen, S. (2006). ON-CHIP ESD PROTECTION FOR RFICS. In: ISMAIL, M., GONZÁLEZ, D.R. (eds) Radio Design in Nanometer Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-4824-1_9
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DOI: https://doi.org/10.1007/978-1-4020-4824-1_9
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