Abstract
Phase-locked loops (PLLs) are used to implement a variety of timing related functions, such as frequency synthesis and clock/data recovery. Previously, PLL designers have been preoccupied with optimizing one or several PLL parameters to achieve the best performance. More recently however, the challenge has shifted to building affordable radios by seamless integration of different circuit blocks. This includes building the PLL block in deep-submicron process nodes that are hostile to pure RF and analog circuit techniques. In this chapter, different challenges in the design of PLLs in deep submicron technology to address the growing need for developing multi-band radios and realizing high data rate communication systems will be explored. Furthermore, some of the digital techniques and architectures for designing PLLs that are now becoming more ubiquitous in digital centric process technologies will be examined.
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Khalil, W., Bakkaloglu, B. (2006). CHALLENGES IN THE DESIGN OF PLLS IN DEEP-SUBMICRON TECHNOLOGY. In: ISMAIL, M., GONZÁLEZ, D.R. (eds) Radio Design in Nanometer Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-4824-1_12
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DOI: https://doi.org/10.1007/978-1-4020-4824-1_12
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