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Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion

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Analog Circuit Design

Abstract

A novel implementation for algorithmic and pipelined ADCs is presented in this paper. A floating voltage hold buffer is proposed which enables the accurate addition of signal voltages without requiring precisely matching and linear components. A new 1.5-bit stage is presented based on the floating hold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3.3 MS/s algorithmic ADC in 0.25μm standard CMOS for a 2V application is described. It occupies O.15mm2 of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit algorithmic ADC stages.

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Author information

Authors and Affiliations

  1. Xilinx, IC design, Citywest Business Campus, Logic Drive, Saggart, Dublin, Ireland

    Patrick J. Quinn & Maxim P. Pribytko

  2. Department of Electrical Engineering, Eindhoven University of Technology, 5600 MB, Eindhoven, The Netherlands

    Arthur H. M. van Roermund

Authors
  1. Patrick J. Quinn
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  2. Maxim P. Pribytko
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  3. Arthur H. M. van Roermund
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Editor information

Editors and Affiliations

  1. Delft University of Technology, The Netherlands

    J. H. Huijsing

  2. KU Leuven, Belgium

    Michiel Steyaert

  3. Eindhoven University of Technology, The Netherlands

    Arthur van Roermund

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© 2004 Springer Science+Business Media New York

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Quinn, P.J., Pribytko, M.P., van Roermund, A.H.M. (2004). Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion. In: Huijsing, J.H., Steyaert, M., van Roermund, A. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4020-2805-2_15

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  • DOI: https://doi.org/10.1007/978-1-4020-2805-2_15

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5253-0

  • Online ISBN: 978-1-4020-2805-2

  • eBook Packages: Springer Book Archive

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