The Platform as an Interface in a Soc Design Curriculum

Abstract

The steady increase of complexity of single chip systems drives the search for restricting the design space in meaningful ways. The trick is to restrict the design space such that the design process becomes fast and efficient while the resulting product is still close to optimal. One widely used way to do this is to provide architectural templates that allow to quickly assemble a large number of components in a very systematic way. The recent trend to platform based design [1,2,3] is emerging because it is increasingly difficult to organize a large number of pre-designed intellectual property (IP) blocks on chip. Nexperia [4,5] is a successful example of a platform. As figure 1 shows, a typical instance of the platform may consist of a RISC and a VLIW media processor, four buses, a central memory controller and a fairly large number of dedicated functional blocks. It is much easier to start with a platform like this and optimise and fine tune it for a particular product, than to start from scratch. Also, analysis and design tools can be developed for the platform and reused for every product development, which is a significant advantage because the development of specific tools is typically far beyond the possibilities of individual design projects.