CMOS Devices Lifetime Prediction Method

Abstract

Hot carrier induced degradation of MOSFET performance versus time is an important reliability concern in modern microcircuits. The development of reliability tools which aim to predict the degradation in circuit performance after a specified operating period is also a considerable interest within the semiconductor industry [1]. The concept of Design For Reliability (DFR) is a new challenge. Design For Reliability strategy is based on reliability simulation in the design flow that aims to predict the impact of physical phenomena from MOSFET to IC electrical characteristics over the operating time. Consequently, reliability tools need to take into account reliability models of transistor. The challenge for reliability simulation is to link the physical degradation mechanisms on the electrical characteristics of an electronic system from the transistor level to the circuit level or system level [2]. The major requirement in term of reliability simulation is to calibrate transistor device reliability model based on experimental case study [3]. A synthesis of such transistor device reliability models is proposed concerning CMOS process technology versus a wear-out failure : hot-carrier injection. A discussion is introduced about how using these device reliability models to analyse circuit level reliability. This paper is an approach dedicated to masters student people to get knowledge to better apprehend semi-conductor device reliability by electrical simulation at the transistor level. This work could be included in microelectronics education course focusing on semi-conductor device reliability in complementary of integrated circuits design.