An Open System-on-Chip Platform for Education

Abstract

Million-gate integrated circuits are increasingly being designed as system-on-chip (SoC) platforms since platform design mitigates the risks involved with integrating a CPU core and other virtual components by a fixed deadline. Using this approach, designers can overcome uncertainties about the quality of the components and their interaction and can produce derivative designs rapidly. The development of a SoC platform is described in this paper. In the process of conducting this team project, students learned not only to reuse existing cores but also the requirements to create high quality cores for reuse. The SoC platform, which uses only open cores that can be obtained by anyone at no charge, can also serve as an “industrial strength” design for students to learn about optimizations at the logic and physical levels. Thus, students can exercise synthesis and place/route tools to explore the power-delayarea solution space of a million-gate design. Having internal visibility of the components at both the source code level and at the physical layout level greatly facilitates their understanding of SoC issues. The SoC platform is being placed in the public domain so that others may contribute to its enhancement.