Abstract
This paper presents a design représentation based on planar graph and dual graph. Substructures are represented by vertices and physical connections and signal transmission between substructures are represented by edges. By testing planarity of a graph, designers can evaluate the electronic circuit and material compatibility of embedded substructures and interconnected substructures. By generating dual graph, designers can develop the optimal layout of the electronic circuit and substructures. This graph représentation allows for concurrent design and programming at both System level and Subsystem level.
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Hou, Y., Ji, L., Jin, D. (2004). Graph Based Representation in Design of Multifunctional Structure. In: Yan, XT., Jiang, CY., Juster, N.P. (eds) Perspectives from Europe and Asia on Engineering Design and Manufacture. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-2212-8_8
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DOI: https://doi.org/10.1007/978-1-4020-2212-8_8
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-015-7003-9
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