Abstract
In chapter 1, layout synthesis was defined as ‘the generation of the physical layout of a design from a corresponding abstract structural description’. In recent years, considerable interest has been generated in the development of suitable tools for the layout of logic networks for ASIC implementation. The facilities provided by these tools are usually dependent on the chosen implementation technology and design style. Automatic layout systems are commonly used for both gate array and standard cell design styles (Soukup, 1981).
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3.5 References
De Micheli, G. and Sangiovanni-Vincentelli, A. L. (1983). ‘Multiple constrained folding of programmable logic arrays: theory and applications’, IEEE Transactions on Computer-Aided Design, CAD-2(3), pp. 151–167.
De Micheli, G. (1987). ‘Performance-oriented synthesis of large-scale domino CMOS circuits’, IEEE Transactions on Computer-Aided Design, CAD-6(5), pp. 751–764.
Devadas, S. and Newton, A. R. (1987). ‘Topological optimisation of multiple-level array logic’, IEEE Transactions on Computer-Aided Design, CAD-6(6), pp. 915–941.
Dillinger, T. E. (1988). VLSI Engineering, Prentice-Hall.
Egan, J. R. and Liu, C. L. (1984). ‘Bipartite folding and partitioning of a PLA’, IEEE Transactions on Computer-Aided Design, CAD-3 (3), pp. 191–199.
Fleisher, H. and Maissel, L. I. (1975). ‘An introduction to array logic’, IBM Journal of Research and Development, 19, pp. 98–109.
Hachtel, G. D., Newton, A. R. and Sangiovanni-Vincentelli, A. L. (1982). ‘An algorithm for optimal PLA folding’, IEEE Transactions on Computer-Aided Design, CAD-1(2), pp. 63–77.
Hong, Y-S., Park, K-H. and Kim, M. (1989). ‘A heuristic algorithm for ordering the columns in one-dimensional logic arrays’, IEEE Transactions on Computer-Aided Design, 8 (5), pp. 547–562.
Huang, S. and Wing, O. (1989). ‘Improved gate matrix layout’, IEEE Transactions on Computer-Aided Design, 8 (8), pp. 875–889.
Huentemann, F. H. and Baitinger, U. G. (1990). ‘A gate-matrix oriented partitioning approach for multilevel logical networks’, Proceedings of the European Design Automation Conference, pp. 327–331.
Hwang, D. W., Fuchs, W. K. and Kang, S. M. (1987). ‘An efficient approach to gate matrix layout’, IEEE Transactions on Computer-Aided Design, CAD-6(5), pp. 802–808.
Kang, S. M, Krambeck, R. H., Law, H. S. and Lopez, A. D. (1983). ‘Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design’, IEEE Transactions on Computer-Aided Design, CAD-2(1), pp. 18–29.
Lopez, A. D. and Law, H. F. S. (1980). ‘A dense gate matrix layout method for MOS VLSI’, IEEE Transactions on Electron Devices, ED-27 (8), pp. 1671–1675.
Rowen, C. and Hennessy, J. L. (1985), ‘SWAMI: a flexible logic implementation system’, 22nd. Design Automation Conference, pp. 169–175.
Soukup, J. (1981). ‘Circuit layout’, Proceedings of the IEEE, 69 (10), pp. 1281–1304.
Uehara, T. and VanCleemput, W. M. (1981). ‘Optimal layout of CMOS functional arrays’, IEEE Transactions on Computers, C-30 (5), pp. 305–312.
Weinberger, A. (1967). ‘Large scale integration of MOS complex logic: a layout method’, IEEEE Journal of Solid-State Circuits, SC-2 (4), pp. 182–190.
Weste, N. and Eshraghian, K. (1985). Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley.
Wimer, S., Pinter, R. Y. and Feldman, J. A. (1987). ‘Optimal chaining of CMOS transistors in a functional cell’, IEEE Transactions on Computer-Aided Design, CAD-6(5), pp. 795–801.
Wing, O., Huang, S. and Wang, R. (1985). ‘Gate matrix layout’, IEEE Transactions on Computer-Aided Design, CAD-4(3), pp. 220–231.
Wong, D. F., Leong, H. W. and Liu, C. L. (1988). Simulated Annealing for VLSI Design, Kluwer Academic Publishers.
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© 1992 M. D. Edwards
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Edwards, M.D. (1992). Layout Synthesis. In: Automatic Logic Synthesis Techniques for Digital Systems. Macmillan New Electronics Series. Palgrave, London. https://doi.org/10.1007/978-1-349-22267-4_3
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DOI: https://doi.org/10.1007/978-1-349-22267-4_3
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