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Chapter 20

  • L. A. A. Warnes
Chapter

Abstract

1 We note that at all times D2 = Q1 and that D1 = (Q1Q2)’ and that the device is positive-edge triggered. The table of figure A20.1a gives the successive states of the circuit when the initial state is Q1 = Q2 = 1, and the corresponding timing diagram is shown in figure A20.1b. When the initial state is Q1 = Q2 = 0, the successive states are shown in figure A20.1c, from which we see that the former sequence repeats.

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Copyright information

© L.A.A. Warnes 1994

Authors and Affiliations

  • L. A. A. Warnes
    • 1
  1. 1.Department of Electronic and Electrical EngineeringLoughborough University of TechnologyUK

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