Distribution of D.C. Power to Logic

Abstract

In a digital system, sudden massive changes of load current in the power supply serving the logic can easily occur. For instance, it is not uncommon for a 32-bit word of data to be gated on to 32 parallel signal lines. If the word happens to be ‘all ones’, the amount of current suddenly switched out of the +5 V supply is quite large. For instance, if the lines are shunt terminated in their characteristic impedance of 100 Ω, the total current switched, at 50 mA per line for a 5 V signal, is 1.6 A. We see what a massive event this is when we assume a reasonable risetime for the signal, say 5 ns, and find that the rate of change of current out of the supply

$$ \frac{{{d_i}}}{{{d_t}}} = \frac{{1.6}}{{5x{{10}^{ - 9}}}}A/s = 320x{10^6}\,A/s $$

For proper functioning of the logic it is important that such a massive, rapid current demand should not cause a significant drop in the voltage bus in the vicinity of the demand at any time after that demand has occurred. (A 50 mV drop could be regarded as the maximum acceptable.)