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Machine-Code Generation

  • Torben Ægidius Mogensen
Part of the Undergraduate Topics in Computer Science book series (UTICS)

Abstract

The intermediate language we have used in Chap.  6 is quite low-level and similar to the type of machine code you can find on modern RISC processors, with a few exceptions: We have used an unbounded number of variables, where a processor will have a bounded number of registers, we have used high-level instructions for function definitions, calls and return, we have assumed that any constant can be an operand to an arithmetic instruction. Typically, RISC processors allow only small constants as operands, and in the intermediate language, the IF-THEN-ELSE instruction has two target labels, where, on most processors, the conditional jump instruction has only one target label, and simply falls through to the next instruction when the condition is false. The problem of mapping a large set of variables to a small number of registers is handled by register allocation, as explained in Chap.  8. Functions are treated in Chap.  9. We will look at the remaining two problems in this chapter.

Keywords

Instruction Sequence Destination Register Target Label Register Allocation Machine Code 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag London Limited 2011

Authors and Affiliations

  1. 1.Department of Computer ScienceUniversity of CopenhagenCopenhagenDenmark

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