Automating the Analysis of Wafer Data Using Adaptive Resonance Theory Networks

  • Emilio Miguelañez
  • Ali M S Zalzala
  • Paul Tabor
Conference paper


In semiconductor manufacturing, finding needles in haystacks is easy compared with finding sub micron defects in modern ICs like complex microprocessors. The problem is likely to grow much worse as the relative complexity of chips (number of transistors and total wiring length) increases as the size of the smallest defects that can cause failures decreases. The use of unsupervised learning is a promising strategy towards the development of fully automated classification tools. This research intends to develop an automatic defect classification system for electrical test analysis of semiconductor wafer using an adaptive resonance theory network as a classifier. As a primary input source to the network, the system employs ebinmaps obtained from the test stage of the manufacturing process. To accomplish this task, a filtering algorithm is also implemented able to discard those wafermaps without pattern. This paper reports satisfactory results showing that the proposed system can recognised defect spatial patterns with a 82% correct e-binmap classification rate.


Edge Effect Pattern Miner Ring Effect Adaptive Resonance Theory Semiconductor Wafer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    T. Hattori, Detection and Identification of Particles on silicon Surfaces, Particles on Surfaces, Detection, Adhesion, and Removal, Edited by K.L. Mittal, Marcel Dekker, Inc., New York.Google Scholar
  2. 2.
    K. W. Tobin, S. S. Gleason, F. Lakhami, and M. H. Bennet, (1997) Automated Analysis for Rapid Defect Sourcing and Yield Learning. Future Fab International, Vol. 4.Google Scholar
  3. 3.
    The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, 2001.Google Scholar
  4. 4.
    M. M. Slama, M. H. Bennett, and P. W. Fletcher, (1992) Advanced In-Line Process Control of Defects. Integrated Circuit Metrology, Inspection, and Process Control VI, SPIE vol. 1673, p. 496.Google Scholar
  5. 5.
    B. Trafas, M. H. Bennet, M. Godwin, (1995) Meeting Advanced Pattern Inspection System Requirements for 0.25-μm Technology and Beyond. Microelectronic Manufacturing Yield Reliability, and Failure Analysis, SPIE vol. 2635, p. 50.Google Scholar
  6. 6.
    R. Sherman, E. Tirosh, Z. Smilansky, (1993) Automatic Defect Classification System for Semiconductor Wafers. Machine Vision Applications in Industrial Inspections, SPIE Vol. 1907, p.72.Google Scholar
  7. 7.
    P. B. Chou, A. R. Rao, M. C. Sturzenbecker, F. Y. Wu, V. H. Brecher, (1997) Automatic Defect Classification for Semiconductor Manufacturing. Machine Vision and Applications, Vol. 9(4), p. 201.CrossRefGoogle Scholar
  8. 8.
    K. W. Tobin, S. S.Gleason, T. P. Karnowski, and S. L. Cohen, (1997) Feature Analysis and Classification of Manufacturing Signatures on Semiconductor Wafers. SPIE 9th Annual Symposium on Electronic Imaging: Science and Technology, San Jose, CA.Google Scholar
  9. 9.
    K. W. Tobin, S. S. Gleason, T. P. Karnowski, S. L. Cohen and F. Lakhani, (1997) Automatic Classification of Spatial Signatures on Semiconductor Wafermaps. SPIE 22nd Annual International Symposium on Microlithography, Santa Clara Convention Center, Santa Clara, CA.Google Scholar
  10. 10.
    K. W. Tobin, S. S. Gleason, T. P. Karnowski and M. H. Bennett, (1996) An Image Paradigm for Semiconductor Defect Data Reduction, SPIE’s 1996 International Symposium on Microlithography, Santa Clara, CA.Google Scholar
  11. 11.
    S. S. Gleason, K. W. Tobin, T. P. Karnowski, and Fred Lakhani, (1999) Rapid Yield Learning through Optical Defect and Electrical Test Analysis. SPIE’s Metrology, Inspection, and Process Control for Microlithography XII, Santa Clara Convention Center, Santa Clara, CA.Google Scholar
  12. 12.
    S. S. Gleason, K. W. Tobin and T. P. Karnowski, (1997) An Integrated Spatial Signature Analysis and Automatic Defect Classification System. 191st Meeting of The Electrochemical Society, Inc.Google Scholar
  13. 13.
    T. P. Karnowski, K. W. Tobin, S. S. Gleason, Fred Lakhani, (1999) The Application of Spatial Signature Analysis to Electrical Test Data: Validation Study. SPIE’s 24th Annual International Symposium on Metrology, Inspection and Process Control for Microlithography XIII, Santa Clara Convention Center, Santa Clara, CA.Google Scholar
  14. 14.
    Bennett, M. H., Tobin, K. W., Gleason, S. S., (1995) Automatic Defect Classification: Status and Industry Trends. Integrated Circuit Metrology, Inspection, and Process Control IX, Proc. SPIE, Vol. 2439, p. 210–220.Google Scholar
  15. 15.
    F. Chen and S. Liu, (2000) A Neural-Network Approach To Recognize Defect Spatial Pattern In Semiconductor Fabrication. IEEE Transactions on Semiconductor Manufacturing, Vol. 13(3).Google Scholar
  16. 16.
    Carpenter, G. A. and S. Grossberg, (1998) The ART of adaptive pattern recognition by self-organization neural network. Computer, vol. 21, no. 3, pp. 77–88.CrossRefGoogle Scholar
  17. 17.
    Lim, Jae S. (1990) Two-Dimensional Signal and Image Processing. Englewood Cliffs, NJ: Prentice Hall, pp. 469–476.Google Scholar
  18. 18.
    A. Canuto, M. Fairhurst and G. Howells, (2001) Improving ARTMap learning through variable vigilance. International Journal of Neural Systems, Vol. 11, No. 6, pp. 509–522Google Scholar
  19. 19.
    W. H. Highleyman, (1962) The Design and analysis of pattern recognition experiments. Bell Systems Technical Journal, vol. 41, p. 723–744, 1962.Google Scholar
  20. 20.
    B. D. Ripley, (1996) Pattern Recognition and Neural Networks, Cambridge University Press, p. 75.Google Scholar
  21. 21.
    K. Kameyana, and Y. Kosugi, (1999) Semiconductor Defect Classification using Hyperellipsoid Clustering Neural Networks and Model Switching. International Joint Conference on Neural Networks, Vol. 5, p. 3505–3510.Google Scholar
  22. 22.
    Kohonen, T., (1998) Self organization and associative memory. 3rd Ed, New York Springer-Verlag.Google Scholar
  23. 23.
    Kohonen T., (1990) The self-organizing map. Proceedings of the IEEE 78, pp. 1464–1480.Google Scholar

Copyright information

© Springer-Verlag London 2004

Authors and Affiliations

  • Emilio Miguelañez
    • 1
  • Ali M S Zalzala
    • 1
  • Paul Tabor
    • 2
  1. 1.Department of ElectricalElectronic and Computer Engineering School of Engineering and Physical Sciences Heriot-Watt UniversityEdinburghUK
  2. 2.Test Advantage, IncTempe, ArizonaUSA

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